Abstract: A semiconductor device provided with a first cooling fan and heat-radiating fins is mounted on a board, and there is provided a second cooling fan for supplying cooling air to the board, such that a flow passage is formed for directing the cooling air, supplied from the second cooling fan, toward the board through the first cooling fan.

Abstract: A control circuit of a memory system including a dynamic random access memory may include a first integrated circuit formed on a common substrate. The first integrated circuit may include a circuit responsive to an external memory access request signal for generating a control signal for controlling an operation timing of the dynamic random access memory to supply the control signal to the dynamic random access memory and a circuit for generating an address signal for specifying an address of the dynamic random access memory to be accessed to supply the address signal to the dynamic random access memory. A second integrated circuit includes a read/write circuit for reading data from the dynamic random access memory and for writing data in the dynamic random access memory.

Abstract: Method and apparatus for testing a memory mounted on an information processing system which includes a processor and at least one memory device. The memory device has a built-in memory test capability. In testing the memory mounted on the system, a test using the built-in test capability is combined with an additional test using a normal write/read operation of the memory performed by the processor unit. While the test using the built-in test capability is performed over the entire memory addresses, the additional test is performed with limited addresses.

Abstract: In a partial write control apparatus for a memory having a high speed operation mode such as a nibble mode or a page mode, when a partial write request for a plurality of words including those which require partial write is received, a memory control signal generator causes the memory to read successively all the words requiring partial write in a single high speed operation mode read cycle. A merging circuit merges those portions of the read-out words which need no alteration with write data and forms a group of updated complete words. Then, the memory control signal generator causes the memory to write successively these words in a single high speed operation mode write cycle.

Abstract: A control circuit of a memory system including a dynamic random access memory may include a first integrated circuit formed on a common substrate. The first integrated circuit may include a circuit responsive to an external memory access request signal for generating a control signal for controlling an operation timing of the dynamic random access memory to supply the control signal to the dynamic random access memory and a circuit for generating an address signal for specifying an address of the dynamic random access memory to be accessed to supply the address signal to the dynamic random access memory. A second integrated circuit includes a read/write circuit for reading data from the dynamic random access memory and for writing data in the dynamic random access memory.