Abstract: In a distributed information communication processing system in which a plurality of information communication devices provides a service through a network, response speed, electric power consumption, and further reliability are improved. The distributed information communication processing system which provides various services is configured by associating an entrance node (EN) which executes filtering near sensors, actuators, and terminals being information sources, an intelligent node (IN) which changes an information processing position and executes information processing and communication processing instead of a data center (DC), and a management node (MN) which manages these nodes. Thereby, real time type information processing can be realized.

Abstract: A system permitting alteration of the information processing position, where an existing information system is used, while minimizing alterations in configuration or the like, is to be provided. Intelligent nodes each having an information processing section and any desired address altering section are arranged on boundaries of a network where packets are likely to pass. This node has a flow table for recognizing as a flow a group of packets transmitted from each user's terminal, a flow status table for determining the connection state and the next destination address or the final destination address of each flow, and a module to observe the loaded state of its own information processing function. It rewrites the destination address of any flow not in a connection-established state in the flow status table to a less loaded one out of its own information processing function section or external information processing apparatus.

Abstract: In a distributed information communication processing system in which a plurality of information communication devices provides a service through a network, response speed, electric power consumption, and further reliability are improved. The distributed information communication processing system which provides various services is configured by associating an entrance node (EN) which executes filtering near sensors, actuators, and terminals being information sources, an intelligent node (IN) which changes an information processing position and executes information processing and communication processing instead of a data center (DC), and a management node (MN) which manages these nodes. Thereby, real time type information processing can be realized.

Abstract: An object of the present invention is to enhance the followability of the automatic scaling of a whole system corresponding to an increase of requests in a service linkage system for linking plural services. A cloud that executes intermediate service receives an estimate of the output of service at a previous stage by an output rate estimating unit and an information gathering response from a cloud management server, estimates an output rate, and outputs the estimate to service at a following stage. A scaling control unit receives the estimate of the output of the service at the previous stage and the information gathering response, determines resources allocated to the intermediate service, and outputs a scaling request to the cloud management server and the output rate estimating unit.

Abstract: A system permitting alteration of the information processing position, where an existing information system is used, while minimizing alterations in configuration or the like, is to be provided. Intelligent nodes each having an information processing section and any desired address altering section are arranged on boundaries of a network where packets are likely to pass. This node has a flow table for recognizing as a flow a group of packets transmitted from each user's terminal, a flow status table for determining the connection state and the next destination address or the final destination address of each flow, and a module to observe the loaded state of its own information processing function. It rewrites the destination address of any flow not in a connection-established state in the flow status table to a less loaded one out of its own information processing function section or external information processing apparatus.

Abstract: Barrier synchronization between multiprocessors is performed at high speed while reducing overhead of parallel processing without adding any special hardware mechanism. A parallel computer synchronization method is provided to synchronize threads through barrier synchronization for parallel execution of plural threads on plural processor modules. The parallel computer has plural processor modules (P0 and P1) equipped with plural processor cores (cpu0 to cpu3). The processor cores are each assigned plural threads (Th0 to Th7) to execute multithread processing. The plural threads (Th0 to Th7) are set in hierarchical groups (Gr), and barrier synchronization is performed on each group separately.

Abstract: Non-speculatively prefetched data is prevented from being discarded from a cache memory before being accessed. In a cache memory including a cache control unit for reading data from a main memory into the cache memory and registering the data in the cache memory upon reception of a fill request from a processor and for accessing the data in the cache memory upon reception of a memory instruction from the processor, a cache line of the cache memory includes a registration information storage unit for storing information indicating whether the registered data is written into the cache line in response to the fill request and whether the registered data is accessed by the memory instruction. The cache control unit sets information in the registration information storage unit for performing a prefetch based on the fill request and resets the information for accessing the cache line based on the memory instruction.

Abstract: To exchange data between adjacent nodes at high speed while using an existing network including a fat tree and a multistage crossbar switch. This invention provides a parallel computer system including: a plurality of nodes each of which includes a processor and a communication unit; a switch for connecting the plurality of nodes with each other; a first network for connecting each of the plurality of nodes and the switch; and a second network for partially connecting the plurality of nodes with each other. Further, the first network is comprised of one of a fat tree and a multistage crossbar network. Further, the second network partially connects predetermined nodes among the plurality of nodes directly with each other.

Abstract: When the same data is used in a multiprocessor system, cache misses are reduced to prevent a coherence request from frequently occurring between processors.

Abstract: A processor system capable of improving usability and performance of an on-chip heterogeneous multiprocessor is provided. The processor system has a processor and a memory, the processor including one control unit that reads a program, a plurality of arithmetic units that transmit a SIMD instruction of the program read by the control unit, and a shared cache capable of storing the program read by the control unit from the memory and allowing the control unit and the plurality of arithmetic units to read and write data. An instruction transmitted from the control unit to the plurality of arithmetic units specifies, in a process where the plurality of arithmetic units execute instructions, whether, until receiving an external signal from an arithmetic unit different from the arithmetic unit that is executing the instruction, execution of the instruction is to be suspended.

Abstract: Barrier synchronization between multiprocessors is performed at high speed while reducing overhead of parallel processing without adding any special hardware mechanism. A parallel computer synchronization method is provided to synchronize threads through barrier synchronization for parallel execution of plural threads on plural processor modules. The parallel computer has plural processor modules (P0 and P1) equipped with plural processor cores (cpu0 to cpu3). The processor cores are each assigned plural threads (Th0 to Th7) to execute multithread processing. The plural threads (Th0 to Th7) are set in hierarchical groups (Gr), and barrier synchronization is performed on each group separately.

Abstract: It is possible to simplify a transaction for maintaining cache coherency in a shared-memory multiprocessor. A directory is provided that has a bit train indicating, for each of the pages of a main memory, whether the page is registered in a cache of each node group (zero when not registered). A processor has an instruction to clear a directory entry corresponding to a specified page to zero. A contracting device monitors a transaction for maintaining cache coherency that flows through an interconnection network, and it detects bits in the directory that can be set to zero.

Abstract: Disclosed is a memory system which comprises a first cache memory of a high rank close to a processor; a second cache memory or a main memory device of a lower rank; a first table for storing a line address when there is no line data in the first cache memory at a time of making a transfer request for the line data and the transfer request for the line data is made to the second cache memory or the main memory device; and means for comparing a line address registered in the first table with a line address of a transfer destination every time the transfer request is made. When a result of comparison of the line address in the first table is a miss-hit, the line address of the transfer destination is registered in the first table and it is indicated whether the result of comparison of the line address in the first table is a hit or miss-hit.

Abstract: Disclosed is a memory system which comprises a first cache memory of a high rank close to a processor; a second cache memory or a main memory device of a lower rank; a first table for storing a line address when there is no line data in the first cache memory at a time of making a transfer request for the line data and the transfer request for the line data is made to the second cache memory or the main memory device; and means for comparing a line address registered in the first table with a line address of a transfer destination every time the transfer request is made. When a result of comparison of the line address in the first table is a miss-hit, the line address of the transfer destination is registered in the first table and it is indicated whether the result of comparison of the line address in the first table is a hit or miss-hit.