Patents by Inventor Hidetaka Fukudome

Hidetaka Fukudome has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9236184
    Abstract: In a method for manufacturing a monolithic ceramic electronic component, when an inner conductor is formed by printing an electrically conductive paste, a smear may be generated in an opening of the inner conductor at a side of the opening near to a position from which printing is started in a printing direction. The smear may cause an unwanted contact between the inner conductor and a via conductor, which is a conductor extending through the opening and having a potential different from that of the inner conductor, so as to cause a short-circuit. The inner conductor is printed such that the center of each via conductor is deviated from the center of the opening in the direction in which the electrically conductive paste is printed. With this structure, even if the smear is generated in the opening, the probability of a short-circuit is minimized.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: January 12, 2016
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hidetaka Fukudome
  • Publication number: 20130091701
    Abstract: In a method for manufacturing a monolithic ceramic electronic component, when an inner conductor is formed by printing an electrically conductive paste, a smear may be generated in an opening of the inner conductor at a side of the opening near to a position from which printing is started in a printing direction. The smear may cause an unwanted contact between the inner conductor and a via conductor, which is a conductor extending through the opening and having a potential different from that of the inner conductor, so as to cause a short-circuit. The inner conductor is printed such that the center of each via conductor is deviated from the center of the opening in the direction in which the electrically conductive paste is printed. With this structure, even if the smear is generated in the opening, the probability of a short-circuit is minimized.
    Type: Application
    Filed: April 3, 2012
    Publication date: April 18, 2013
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventor: Hidetaka FUKUDOME
  • Patent number: 8174815
    Abstract: In a method for manufacturing a monolithic ceramic electronic component, when an inner conductor is formed by printing an electrically conductive paste, a smear may be generated in an opening of the inner conductor at a side of the opening near to a position from which printing is started in a printing direction. The smear may cause an unwanted contact between the inner conductor and a via conductor, which is a conductor extending through the opening and having a potential different from that of the inner conductor, and cause a short-circuit. The inner conductor is printed in such a manner that the center of each of the via conductors is deviated from the center of the opening in the direction in which the electrically conductive paste is printed. With this structure, even if the smear is generated in the opening, the probability that the inner conductor contact the via conductor and cause a short-circuit is minimized.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: May 8, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Hidetaka Fukudome
  • Patent number: 7894202
    Abstract: A multilayer capacitor includes a laminate of ceramic layers, and a capacitor unit provided in the laminate. In the multilayer capacitor, the relationships P?Ra and P?W are established, wherein P represents the average projection height of first and second via conductors from the upper surface, Ra represents the surface roughness of the upper surface, and W represents an amount of curvature of the laminate. Further, the projecting portions of the first and second via conductors projecting from the upper surface are buried in first and second external electrodes, respectively.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: February 22, 2011
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hidetaka Fukudome, Masaaki Taniguchi
  • Publication number: 20100020465
    Abstract: In a method for manufacturing a monolithic ceramic electronic component, when an inner conductor is formed by printing an electrically conductive paste, a smear may be generated in an opening of the inner conductor at a side of the opening near to a position from which printing is started in a printing direction. The smear may cause an unwanted contact between the inner conductor and a via conductor, which is a conductor extending through the opening and having a potential different from that of the inner conductor, and cause a short-circuit. The inner conductor is printed in such a manner that the center of each of the via conductors is deviated from the center of the opening in the direction in which the electrically conductive paste is printed. With this structure, even if the smear is generated in the opening, the probability that the inner conductor contact the via conductor and cause a short-circuit is minimized.
    Type: Application
    Filed: July 17, 2009
    Publication date: January 28, 2010
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventor: Hidetaka FUKUDOME
  • Patent number: 7430107
    Abstract: A monolithic capacitor includes a laminate of ceramic layers, the laminate having first and second surfaces, at least one pair of first and second internal electrodes, first and second external electrodes disposed on the first surface, third and fourth external electrodes disposed on the second surface, a first via conductor that electrically connects the first external electrode to the first internal electrode and to the third external electrode and that contains a metal oxide, and a second via conductor that electrically connects the second external electrode to the second internal electrode and to the fourth external electrode and that contains a metal oxide, wherein, in each of the first and second via conductors, the metal oxide content at an end on the second surface side is higher than the metal oxide content at a center or at an end on the first surface side.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: September 30, 2008
    Assignee: Murata Manufacturing Co., Ltd
    Inventors: Hidetaka Fukudome, Masashi Nishimura, Masaaki Taniguchi, Yoshio Kawaguchi
  • Publication number: 20080043400
    Abstract: A monolithic capacitor includes a laminate of ceramic layers, the laminate having first and second surfaces, at least one pair of first and second internal electrodes, first and second external electrodes disposed on the first surface, third and fourth external electrodes disposed on the second surface, a first via conductor that electrically connects the first external electrode to the first internal electrode and to the third external electrode and that contains a metal oxide, and a second via conductor that electrically connects the second external electrode to the second internal electrode and to the fourth external electrode and that contains a metal oxide, wherein, in each of the first and second via conductors, the metal oxide content at an end on the second surface side is higher than the metal oxide content at a center or at an end on the first surface side.
    Type: Application
    Filed: August 10, 2007
    Publication date: February 21, 2008
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Hidetaka Fukudome, Masashi Nishimura, Masaaki Taniguchi, Yoshio Kawaguchi
  • Publication number: 20080037199
    Abstract: A multilayer capacitor includes a laminate of ceramic layers, and a capacitor unit provided in the laminate. In the multilayer capacitor, the relationships P?Ra and P?W are established, wherein P represents the average projection height of first and second via conductors from the upper surface, Ra represents the surface roughness of the upper surface, and W represents an amount of curvature of the laminate. Further, the projecting portions of the first and second via conductors projecting from the upper surface are buried in first and second external electrodes, respectively.
    Type: Application
    Filed: August 9, 2007
    Publication date: February 14, 2008
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Hidetaka FUKUDOME, Masaaki TANIGUCHI
  • Publication number: 20050269013
    Abstract: A first laminate block including inner conductors is manufactured, and thin holes are formed in the first laminate block so as to extend between top and bottom surfaces of the first laminate block. The thin holes are filled with conductive paste to form via holes. Then, a ceramic sheet layer is laminated on the bottom surface of the first laminate block, and a second laminate block including inner conductors is laminated on the bottom surface of the ceramic sheet layer to obtain a laminate body. Then, thin holes are formed in the laminate body so as to extend between top and bottom surfaces of the laminate body, and are filled with conductive paste to obtain through via hole.
    Type: Application
    Filed: June 1, 2005
    Publication date: December 8, 2005
    Inventors: Hidetaka Fukudome, Masaaki Taniguchi, Yoshio Kawaguchi