Patents by Inventor Hidetaka Fukudome
Hidetaka Fukudome has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9236184Abstract: In a method for manufacturing a monolithic ceramic electronic component, when an inner conductor is formed by printing an electrically conductive paste, a smear may be generated in an opening of the inner conductor at a side of the opening near to a position from which printing is started in a printing direction. The smear may cause an unwanted contact between the inner conductor and a via conductor, which is a conductor extending through the opening and having a potential different from that of the inner conductor, so as to cause a short-circuit. The inner conductor is printed such that the center of each via conductor is deviated from the center of the opening in the direction in which the electrically conductive paste is printed. With this structure, even if the smear is generated in the opening, the probability of a short-circuit is minimized.Type: GrantFiled: April 3, 2012Date of Patent: January 12, 2016Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Hidetaka Fukudome
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Publication number: 20130091701Abstract: In a method for manufacturing a monolithic ceramic electronic component, when an inner conductor is formed by printing an electrically conductive paste, a smear may be generated in an opening of the inner conductor at a side of the opening near to a position from which printing is started in a printing direction. The smear may cause an unwanted contact between the inner conductor and a via conductor, which is a conductor extending through the opening and having a potential different from that of the inner conductor, so as to cause a short-circuit. The inner conductor is printed such that the center of each via conductor is deviated from the center of the opening in the direction in which the electrically conductive paste is printed. With this structure, even if the smear is generated in the opening, the probability of a short-circuit is minimized.Type: ApplicationFiled: April 3, 2012Publication date: April 18, 2013Applicant: MURATA MANUFACTURING CO., LTD.Inventor: Hidetaka FUKUDOME
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Patent number: 8174815Abstract: In a method for manufacturing a monolithic ceramic electronic component, when an inner conductor is formed by printing an electrically conductive paste, a smear may be generated in an opening of the inner conductor at a side of the opening near to a position from which printing is started in a printing direction. The smear may cause an unwanted contact between the inner conductor and a via conductor, which is a conductor extending through the opening and having a potential different from that of the inner conductor, and cause a short-circuit. The inner conductor is printed in such a manner that the center of each of the via conductors is deviated from the center of the opening in the direction in which the electrically conductive paste is printed. With this structure, even if the smear is generated in the opening, the probability that the inner conductor contact the via conductor and cause a short-circuit is minimized.Type: GrantFiled: July 17, 2009Date of Patent: May 8, 2012Assignee: Murata Manufacturing Co., Ltd.Inventor: Hidetaka Fukudome
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Patent number: 7894202Abstract: A multilayer capacitor includes a laminate of ceramic layers, and a capacitor unit provided in the laminate. In the multilayer capacitor, the relationships P?Ra and P?W are established, wherein P represents the average projection height of first and second via conductors from the upper surface, Ra represents the surface roughness of the upper surface, and W represents an amount of curvature of the laminate. Further, the projecting portions of the first and second via conductors projecting from the upper surface are buried in first and second external electrodes, respectively.Type: GrantFiled: August 9, 2007Date of Patent: February 22, 2011Assignee: Murata Manufacturing Co., Ltd.Inventors: Hidetaka Fukudome, Masaaki Taniguchi
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Publication number: 20100020465Abstract: In a method for manufacturing a monolithic ceramic electronic component, when an inner conductor is formed by printing an electrically conductive paste, a smear may be generated in an opening of the inner conductor at a side of the opening near to a position from which printing is started in a printing direction. The smear may cause an unwanted contact between the inner conductor and a via conductor, which is a conductor extending through the opening and having a potential different from that of the inner conductor, and cause a short-circuit. The inner conductor is printed in such a manner that the center of each of the via conductors is deviated from the center of the opening in the direction in which the electrically conductive paste is printed. With this structure, even if the smear is generated in the opening, the probability that the inner conductor contact the via conductor and cause a short-circuit is minimized.Type: ApplicationFiled: July 17, 2009Publication date: January 28, 2010Applicant: MURATA MANUFACTURING CO., LTD.Inventor: Hidetaka FUKUDOME
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Patent number: 7430107Abstract: A monolithic capacitor includes a laminate of ceramic layers, the laminate having first and second surfaces, at least one pair of first and second internal electrodes, first and second external electrodes disposed on the first surface, third and fourth external electrodes disposed on the second surface, a first via conductor that electrically connects the first external electrode to the first internal electrode and to the third external electrode and that contains a metal oxide, and a second via conductor that electrically connects the second external electrode to the second internal electrode and to the fourth external electrode and that contains a metal oxide, wherein, in each of the first and second via conductors, the metal oxide content at an end on the second surface side is higher than the metal oxide content at a center or at an end on the first surface side.Type: GrantFiled: August 10, 2007Date of Patent: September 30, 2008Assignee: Murata Manufacturing Co., LtdInventors: Hidetaka Fukudome, Masashi Nishimura, Masaaki Taniguchi, Yoshio Kawaguchi
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Publication number: 20080043400Abstract: A monolithic capacitor includes a laminate of ceramic layers, the laminate having first and second surfaces, at least one pair of first and second internal electrodes, first and second external electrodes disposed on the first surface, third and fourth external electrodes disposed on the second surface, a first via conductor that electrically connects the first external electrode to the first internal electrode and to the third external electrode and that contains a metal oxide, and a second via conductor that electrically connects the second external electrode to the second internal electrode and to the fourth external electrode and that contains a metal oxide, wherein, in each of the first and second via conductors, the metal oxide content at an end on the second surface side is higher than the metal oxide content at a center or at an end on the first surface side.Type: ApplicationFiled: August 10, 2007Publication date: February 21, 2008Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Hidetaka Fukudome, Masashi Nishimura, Masaaki Taniguchi, Yoshio Kawaguchi
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Publication number: 20080037199Abstract: A multilayer capacitor includes a laminate of ceramic layers, and a capacitor unit provided in the laminate. In the multilayer capacitor, the relationships P?Ra and P?W are established, wherein P represents the average projection height of first and second via conductors from the upper surface, Ra represents the surface roughness of the upper surface, and W represents an amount of curvature of the laminate. Further, the projecting portions of the first and second via conductors projecting from the upper surface are buried in first and second external electrodes, respectively.Type: ApplicationFiled: August 9, 2007Publication date: February 14, 2008Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Hidetaka FUKUDOME, Masaaki TANIGUCHI
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Publication number: 20050269013Abstract: A first laminate block including inner conductors is manufactured, and thin holes are formed in the first laminate block so as to extend between top and bottom surfaces of the first laminate block. The thin holes are filled with conductive paste to form via holes. Then, a ceramic sheet layer is laminated on the bottom surface of the first laminate block, and a second laminate block including inner conductors is laminated on the bottom surface of the ceramic sheet layer to obtain a laminate body. Then, thin holes are formed in the laminate body so as to extend between top and bottom surfaces of the laminate body, and are filled with conductive paste to obtain through via hole.Type: ApplicationFiled: June 1, 2005Publication date: December 8, 2005Inventors: Hidetaka Fukudome, Masaaki Taniguchi, Yoshio Kawaguchi