Patents by Inventor Hidetaka Horiuchi

Hidetaka Horiuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of reducing coupling between floating gates in nonvolatile memory
    Patent number: 8288225
    Abstract: A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: October 16, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Henry Chien, George Matamis, Tuan Pham, Masaaki Higashitani, Hidetaka Horiuchi, Jeffrey W. Lutze, Nima Mokhlesi, Yupin Kawing Fong
  • METHOD OF REDUCING COUPLING BETWEEN FLOATING GATES IN NONVOLATILE MEMORY
    Publication number: 20110111583
    Abstract: A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.
    Type: Application
    Filed: January 20, 2011
    Publication date: May 12, 2011
    Inventors: Henry Chien, George Matamis, Tuan Pham, Masaaki Higashitani, Hidetaka Horiuchi, Jeffrey W. Lutze, Nima Mokhlesi, Yupin Kawing Fong
  • Method of reducing coupling between floating gates in nonvolatile memory
    Patent number: 7910434
    Abstract: A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: March 22, 2011
    Assignee: SanDisk Corporation
    Inventors: Henry Chien, George Matamis, Tuan Pham, Masaaki Higashitani, Hidetaka Horiuchi, Jeffrey W. Lutze, Nima Mokhlesi, Yupin Kawing Fong
  • METHOD OF REDUCING COUPLING BETWEEN FLOATING GATES IN NONVOLATILE MEMORY
    Publication number: 20100047979
    Abstract: A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.
    Type: Application
    Filed: September 25, 2009
    Publication date: February 25, 2010
    Inventors: Henry Chien, George Matamis, Tuan Pham, Masaaki Higashitani, Hidetaka Horiuchi, Jeffrey W. Lutze, Nima Mokhlesi, Yupin Kawing Fong
  • Methods of reducing coupling between floating gates in nonvolatile memory
    Patent number: 7615445
    Abstract: A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: November 10, 2009
    Assignee: SanDisk Corporation
    Inventors: Henry Chien, George Matamis, Tuan Pham, Masaaki Higashitani, Hidetaka Horiuchi, Jeffrey W. Lutze, Nima Mokhlesi, Yupin Kawing Fong
  • Methods of Reducing Coupling Between Floating Gates in Nonvolatile Memory
    Publication number: 20080076217
    Abstract: A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.
    Type: Application
    Filed: September 21, 2006
    Publication date: March 27, 2008
    Inventors: Henry Chien, George Matamis, Tuan Pham, Masaaki Higashitani, Hidetaka Horiuchi, Jeffrey W. Lutze, Nima Mokhlesi, Yupin Kawing Fong
  • Nonvolatile Memory with Reduced Coupling Between Floating Gates
    Publication number: 20080074920
    Abstract: A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.
    Type: Application
    Filed: September 21, 2006
    Publication date: March 27, 2008
    Inventors: Henry Chien, George Matamis, Tuan Pham, Masaaki Higashitani, Hidetaka Horiuchi, Jeffrey W. Lutze, Nima Mokhlesi, Yupin Kawing Fong
  • Method and apparatus for processing semiconductor substrates
    Patent number: 6558505
    Abstract: Apparatus and methods for producing semiconductor devices are disclosed. A processing chamber includes an interior component having a stepped region including a plurality of raised sections and recessed sections divided by steps. With this apparatus, it is possible to prevent a film of deposited material formed on the stepped region from peeling, thereby decreasing the number of particles in the chamber and increasing the operation rate.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: May 6, 2003
    Assignee: Kawasaki Microelectronics, Inc.
    Inventors: Katsunori Suzuki, Hidetaka Horiuchi, Yasushi Kikuchi, Jin Yokogawa, Ryouichi Kubo, Koji Wakabayashi
  • Method and apparatus for processing semiconductor substrates
    Patent number: 6547921
    Abstract: Apparatus and methods for producing semiconductor devices are disclosed. A processing chamber includes an interior component having a stepped region including a plurality of raised sections and recessed sections divided by steps. With this apparatus, it is possible to prevent a film of deposited material formed on the stepped region from peeling thereby decreasing the number of particles in the chamber and increasing the operation rate.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: April 15, 2003
    Assignee: Kawasaki Microelectronics, Inc.
    Inventors: Katsunori Suzuki, Hidetaka Horiuchi, Yasushi Kikuchi, Jin Yokogawa, Ryouichi Kubo, Koji Wakabayashi
  • Method and apparatus for processing semiconductor substrates
    Publication number: 20030024642
    Abstract: Apparatus and methods for producing semiconductor devices are disclosed. A processing chamber includes an interior component having a stepped region including a plurality of raised sections and recessed sections divided by steps. With this apparatus, it is possible to prevent a film of deposited material formed on the stepped region from peeling, thereby decreasing the number of particles in the chamber and increasing the operation rate.
    Type: Application
    Filed: May 13, 2002
    Publication date: February 6, 2003
    Applicant: Kawasaki Microelectronics, Inc.
    Inventors: Katsunori Suzuki, Hidetaka Horiuchi, Yasushi Kikuchi, Jin Yokogawa, Ryouichi Kubo, Koji Wakabayashi
  • Method and apparatus for processing semiconductor substrates
    Patent number: 6447853
    Abstract: Apparatus and methods for producing semiconductor devices are disclosed. A processing chamber includes an interior component having a stepped region including a plurality of raised sections and recessed sections divided by steps. With this apparatus, it is possible to prevent a film of deposited material formed on the stepped region from peeling, thereby decreasing the number of particles in the chamber and increasing the operation rate.
    Type: Grant
    Filed: November 24, 1999
    Date of Patent: September 10, 2002
    Assignee: Kawasaki Microelectronics, Inc.
    Inventors: Katsunori Suzuki, Hidetaka Horiuchi, Yasushi Kikuchi, Jin Yokogawa, Ryouichi Kubo, Koji Wakabayashi