Patents by Inventor Hidetaka Natsume
Hidetaka Natsume has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9099197Abstract: A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits.Type: GrantFiled: July 9, 2014Date of Patent: August 4, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki Takahashi, Hidetaka Natsume
-
Publication number: 20140321221Abstract: A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits.Type: ApplicationFiled: July 9, 2014Publication date: October 30, 2014Inventors: Hiroyuki TAKAHASHI, Hidetaka NATSUME
-
Patent number: 8797810Abstract: A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits.Type: GrantFiled: February 20, 2014Date of Patent: August 5, 2014Assignee: Renesas Electronics CorporationInventors: Hiroyuki Takahashi, Hidetaka Natsume
-
Publication number: 20140169073Abstract: A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits.Type: ApplicationFiled: February 20, 2014Publication date: June 19, 2014Applicant: Renesas Electronics CorporationInventors: Hiroyuki TAKAHASHI, Hidetaka NATSUME
-
Patent number: 8699284Abstract: A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits.Type: GrantFiled: January 29, 2013Date of Patent: April 15, 2014Assignee: Renesas Electronics CorporationInventors: Hiroyuki Takahashi, Hidetaka Natsume
-
Patent number: 8391084Abstract: A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits.Type: GrantFiled: August 16, 2011Date of Patent: March 5, 2013Assignee: Renesas Electronics CorporationInventors: Hiroyuki Takahashi, Hidetaka Natsume
-
Patent number: 8357612Abstract: A semiconductor device in which a conductor of a bit line may be made as large in thickness as possible to reduce resistance of the bit line and to reduce capacitance across the neighboring bit lines. The device includes a first interlayer film having a first contact metal part accommodated in it, and a second interlayer film. The second interlayer film includes a trench, and is deposited on the first interlayer film. The semiconductor device also includes a metal conductor filled in and protruding above the trench, and a hard mask film deposited on the metal conductor. The semiconductor device also includes sidewalls formed on lateral surfaces of the hard mask film and the metal conductor for overlying the second interlayer film, and a third interlayer film formed above the second interlayer film inclusive of the hard mask film and the sidewalls.Type: GrantFiled: July 2, 2009Date of Patent: January 22, 2013Assignee: Renesas Electronics CorporationInventors: Hiroyuki Hoshizaki, Hidetaka Natsume
-
Publication number: 20110298012Abstract: A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits.Type: ApplicationFiled: August 16, 2011Publication date: December 8, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki TAKAHASHI, Hidetaka NATSUME
-
Patent number: 8036048Abstract: A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits.Type: GrantFiled: October 23, 2008Date of Patent: October 11, 2011Assignee: Renesas Electronics CorporationInventors: Hiroyuki Takahashi, Hidetaka Natsume
-
Patent number: 7660085Abstract: A conventional layout of power supply protective element cannot sufficiently protect an internal circuit against a surge current that flows into a narrow branch line that branches off from a thick main wiring line. A semiconductor device according to an embodiment of the present invention includes a power supply protective element connected around a terminal; a main wiring line connected with a VCC pad or a GND pad; a branch line that branches off from the main wiring line and applies a power supply potential or a ground potential to a functional block of the semiconductor device; a branching portion at which the branch line branches off from the main wiring line; and an internal power supply protective element connected with the branch line.Type: GrantFiled: February 22, 2006Date of Patent: February 9, 2010Assignee: NEC Electronics CorporationInventors: Hiroshi Furuta, Kenji Hibino, Hidetaka Natsume, Toshikatsu Jinbo, Kiyokazu Hashimoto
-
Publication number: 20090273089Abstract: A semiconductor device in which a conductor of a bit line may be made as large in thickness as possible to reduce resistance of the bit line and to reduce capacitance across the neighboring bit lines. The device includes a first interlayer film having a first contact metal part accommodated in it, and a second interlayer film. The second interlayer film includes a trench, and is deposited on the first interlayer film. The semiconductor device also includes a metal conductor filled in and protruding above the trench, and a hard mask film deposited on the metal conductor. The semiconductor device also includes sidewalls formed on lateral surfaces of the hard mask film and the metal conductor for overlying the second interlayer film, and a third interlayer film formed above the second interlayer film inclusive of the hard mask film and the sidewalls.Type: ApplicationFiled: July 2, 2009Publication date: November 5, 2009Applicant: NEC ELECTRONICS CORPORATIONInventors: Hiroyuki Hoshizaki, Hidetaka Natsume
-
Publication number: 20090122595Abstract: A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits.Type: ApplicationFiled: October 23, 2008Publication date: May 14, 2009Applicant: NEC ELECTRONICS CORPORATIONInventors: Hiroyuki TAKAHASHI, Hidetaka NATSUME
-
Patent number: 7250661Abstract: A semiconductor memory device includes first and second source/drain regions, and first and second semiconductor regions. The first source/drain region of a first conductive type is formed in a first well region of a second conductive type for a pair of first MIS-type transistors of the first conductive type. The second source/drain region of the second conductive type is formed in a second well region of the first conductive type for a pair of second MIS-type transistors of the second conductive type. The first semiconductor region of the second conductive type is formed in the first source/drain region. The second semiconductor region of the first conductive type is formed in the second source/drain region.Type: GrantFiled: November 26, 2004Date of Patent: July 31, 2007Assignee: NEC Electronics CorporationInventors: Toshifumi Takahashi, Hidetaka Natsume
-
Patent number: 7214572Abstract: The present invention relates to a semiconductor memory device having a SRAM in which a memory cell comprises a pair of transmission transistors and a flip-flop circuit containing a pair of driver transistors and a pair of load transistors, wherein: a first conductive film interconnection formed from a first conductive film which is set on a semiconductor substrate, constitutes respective gate electrodes of said driver transistors, load transistors and transmission transistors; an inlaid interconnection set in a first insulating film lying on said semiconductor substrate, constitutes one of a pair of local interconnections cross-coupling a pair of input/output terminals in said flip-flop circuit; and a second conductive film interconnection formed from a second conductive film which is set on a second insulating film lying on said first insulating film, constitutes the other one of said pair of local interconnections.Type: GrantFiled: March 28, 2005Date of Patent: May 8, 2007Assignee: NEC Electronics CorporationInventor: Hidetaka Natsume
-
Publication number: 20060187733Abstract: A conventional layout of power supply protective element cannot sufficiently protect an internal circuit against a surge current that flows into a narrow branch line that branches off from a thick main wiring line. A semiconductor device according to an embodiment of the present invention includes a power supply protective element connected around a terminal; a main wiring line connected with a VCC pad or a GND pad; a branch line that branches off from the main wiring line and applies a power supply potential or a ground potential to a functional block of the semiconductor device; a branching portion at which the branch line branches off from the main wiring line; and an internal power supply protective element connected with the branch line.Type: ApplicationFiled: February 22, 2006Publication date: August 24, 2006Inventors: Hiroshi Furuta, Kenji Hibino, Hidetaka Natsume, Toshikatsu Jinbo, Kiyokazu Hashimoto
-
Publication number: 20050224895Abstract: The present invention relates to a semiconductor memory device having a SRAM in which a memory cell comprises a pair of transmission transistors and a flip-flop circuit containing a pair of driver transistors and a pair of load transistors, wherein: a first conductive film interconnection formed from a first conductive film which is set on a semiconductor substrate, constitutes respective gate electrodes of said driver transistors, load transistors and transmission transistors; an inlaid interconnection set in a first insulating film lying on said semiconductor substrate, constitutes one of a pair of local interconnections cross-coupling a pair of input/output terminals in said flip-flop circuit; and a second conductive film interconnection formed from a second conductive film which is set on a second insulating film lying on said first insulating film, constitutes the other one of said pair of local interconnections.Type: ApplicationFiled: March 28, 2005Publication date: October 13, 2005Inventor: Hidetaka Natsume
-
Publication number: 20050116303Abstract: A semiconductor memory device includes first and second source/drain regions, and first and second semiconductor regions. The first source/drain region of a first conductive type is formed in a first well region of a second conductive type for a pair of first MIS-type transistors of the first conductive type. The second source/drain region of the second conductive type is formed in a second well region of the first conductive type for a pair of second MIS-type transistors of the second conductive type. The first semiconductor region of the second conductive type is formed in the first source/drain region. The second semiconductor region of the first conductive type is formed in the second source/drain region.Type: ApplicationFiled: November 26, 2004Publication date: June 2, 2005Applicant: NEC ELECTRONICS CORPORATIONInventors: Toshifumi Takahashi, Hidetaka Natsume
-
Patent number: 6900513Abstract: The present invention relates to a semiconductor memory device having a SRAM in which a memory cell comprises a pair of transmission transistors and a flip-flop circuit containing a pair of driver transistors and a pair of load transistors, wherein: a first conductive film interconnection formed from a first conductive film which is set on a semiconductor substrate, constitutes respective gate electrodes of said driver transistors, load transistors and transmission transistors; an inlaid interconnection set in a first insulating film lying on said semiconductor substrate, constitutes one of a pair of local interconnections cross-coupling a pair of input/output terminals in said flip-flop circuit; and a second conductive film interconnection formed from a second conductive film which is set on a second insulating film lying on said first insulating film, constitutes the other one of said pair of local interconnections.Type: GrantFiled: January 15, 2002Date of Patent: May 31, 2005Assignee: NEC Electronics CorporationInventor: Hidetaka Natsume
-
Patent number: 6765272Abstract: A semiconductor device has a gate electrode which is formed on a first conductive-type well set in semiconductor substrate, with a gate insulating film lying therebetween; a LDD structure in which, on either side of said gate electrode, there are formed a LDD region and a source/drain region; an interlayer insulating film to cover said gate electrode as well as said LDD regions; and contact sections. A contact section connecting to one side of the source/drain regions having a potential equal to a potential of said first conductive-type well is disposed so as to come into contact with the LDD region lying thereunder; and a contact section connecting to the other side of the source/drain region having a potential different from the potential of said first conductive-type well is disposed so as not to come into contact with the LDD region lying thereunder.Type: GrantFiled: April 25, 2002Date of Patent: July 20, 2004Assignee: NEC Electronics CorporationInventor: Hidetaka Natsume
-
Patent number: 6495899Abstract: In a semiconductor device including a semiconductor substrate, a well formed on the semiconductor substrate, and a thick field insulating layer for surrounding an active area of the well, a contact structure is buried in a contact hole provided in the thick field insulating layer and connected to the well, so as to fix a voltage at the well.Type: GrantFiled: March 30, 2001Date of Patent: December 17, 2002Assignee: NEC CorporationInventor: Hidetaka Natsume