Patents by Inventor Hidetake Suzuki

Hidetake Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9663258
    Abstract: According to one embodiment, a stacking/wrapping apparatus includes a stacking device configured to stack paper sheets in a predetermined number on a stacking unit, a wrapping device configured to wrap a bundle of the stacked paper sheets by winding a band thereon, and a transport carrier configured to receive the paper sheet bundle and transport the paper sheet bundle to the wrapping device. The wrapping device includes a hand assembly, a hand drive mechanism configured to open and close the hand assembly and reciprocate the hand assembly at right angles to the stacking direction, and a band winding device configured to wind a wrapper band around the paper sheet bundle drawn into the binding position.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: May 30, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Sakoguchi, Masakazu Itoya, Hidetake Suzuki, Kenichi Hirose
  • Publication number: 20160368632
    Abstract: According to one embodiment, a stacking/wrapping apparatus includes a stacking device configured to stack paper sheets in a predetermined number on a stacking unit, a wrapping device configured to wrap a bundle of the stacked paper sheets by winding a band thereon, and a transport carrier configured to receive the paper sheet bundle and transport the paper sheet bundle to the wrapping device. The wrapping device includes a hand assembly, a hand drive mechanism configured to open and close the hand assembly and reciprocate the hand assembly at right angles to the stacking direction, and a band winding device configured to wind a wrapper band around the paper sheet bundle drawn into the binding position.
    Type: Application
    Filed: June 13, 2016
    Publication date: December 22, 2016
    Inventors: Yoshitaka Sakoguchi, Masakazu Itoya, Hidetake Suzuki, Kenichi Hirose
  • Publication number: 20070000750
    Abstract: A sheet identification apparatus is equipped with a conveying means to convey sheets having sensory objects along the conveying path, a position detecting means to detect positions of sheets conveyed by the conveying means, a plurality of sensors arranged opposing to each other over almost full width in the direction orthogonal to the sheet conveying direction, and a controller to select a sensory object sensor that is capable of detecting the sensory object based on the position data detected by the position detecting means so as to detect the sensory object by the selected sensor.
    Type: Application
    Filed: March 9, 2006
    Publication date: January 4, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Teruhiko Uno, Ryuuji Higashi, Masahito Kochiwa, Hidetake Suzuki
  • Patent number: 6455945
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a plurality of semiconductor chips on a semiconductor substrate, forming a connection part such that the connection part connects the semiconductor chips with other across an dicing line, bonding the semiconductor substrate upon a support substrate, removing the dicing region while maintaining the semiconductor chips in a state such that the semiconductor chips are bonded upon the support substrate, detaching the plurality of semiconductor chips from the support substrate while maintaining an alignment between the semiconductor chips, and separating the semiconductor chips from each other by eliminating the connection part.
    Type: Grant
    Filed: March 18, 1999
    Date of Patent: September 24, 2002
    Assignee: Fujitsu, Limited
    Inventors: Masanori Ishii, Hidetake Suzuki, Yoji Suzuki
  • Patent number: 5919713
    Abstract: A method for fabricating a semiconductor device including the steps of forming a plurality of semiconductor chips on a semiconductor substrate, forming a connection part such that the connection part connects the semiconductor chips with each other across a dicing line, bonding the semiconductor substrate upon a support substrate, removing the dicing region while maintaining the semiconductor chips in a state such that the semiconductor chips are bonded upon the support substrate, detaching the plurality of semiconductor chips from the support substrate while maintaining an alignment between the semiconductor chips, and separating the semiconductor chips from each other by eliminating the connection part.
    Type: Grant
    Filed: December 14, 1994
    Date of Patent: July 6, 1999
    Assignee: Fujitsu Limited
    Inventors: Masanori Ishii, Hidetake Suzuki, Yoji Suzuki
  • Patent number: 5107223
    Abstract: A phase inverter includes first, second, third and fourth terminals, a first coupling circuit coupled between the first and second terminals, a second coupling circuit coupled between the second and third terminals, a third coupling circuit coupled between the third and fourth terminals, and a fourth coupling circuit coupled between the first and fourth terminals. The first to fourth terminals and the first to fourth coupling circuits are arranged into a ring. The first coupling circuit is of a type different from a type of the fourth coupling circuit. The second and third coupling circuits are identical in type. Two output signals having a phase difference of 180.degree. are drawn from the second and fourth terminal when an input terminal is applied to the first terminal, and an output signal is drawn from the first terminal when two input signals having a phase difference of 180.degree. are applied to the second and fourth terminals.
    Type: Grant
    Filed: January 18, 1990
    Date of Patent: April 21, 1992
    Assignee: Fujitsu Limited
    Inventors: Fuminori Sakai, Hidetake Suzuki
  • Patent number: 4910157
    Abstract: A method of producing a compound semiconductor device comprises the steps of: forming a recess portion on a compound semiconductor substrate; forming an ion penetrating mask on the recess portion in such a manner that the surfaces of the compound semiconductor substrate and the ion penetrating mask are level; forming an active layer having a substantially uniform depth is the compound semiconductor by implanting impurity ions into the entire exposed surface and, removing the ion penetrating mask and forming a gate electrode at the recess portion.
    Type: Grant
    Filed: August 23, 1989
    Date of Patent: March 20, 1990
    Assignee: Fujitsu Limited
    Inventors: Yuuichi Hasegawa, Hidetake Suzuki
  • Patent number: 4628338
    Abstract: A compact connection structure between two electrodes made of two types of metals, i.e., metals which respectively make Schottky and ohmic contact with a semiconductor, is provided by using a high melting point metal or silicide thereof which makes Schottky contact with the semiconductor as one electrode metal. The two types of electrodes can be brought into direct contact with each other, enabling elimination of through hole connections between them and therefore increased semiconductor device density.
    Type: Grant
    Filed: September 25, 1985
    Date of Patent: December 9, 1986
    Assignee: Fujitsu Limited
    Inventors: Yoshiro Nakayama, Hidetake Suzuki