Patents by Inventor Hidetaro Nishimura

Hidetaro Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4783597
    Abstract: An ion implant apparatus which forms ions from an ion source into an ion beam to implant the ions into a target to be ion-implanted through an ion beam introduction tube. The ion implant apparatus comprises: radiation means for radiating an electron beam, the radiating means fixed on the ion beam introduction tube; and a target for being radiated by an electron beam, said target reflecting the electron beam to generate a reflectance beam, the electron beam causing a secondary electron beam to be emitted from the electron beam target, the electron beam target being formed so as to prevent the reflectance beam and the secondary electron beam from being directly radiated on the target to be ion-implanted. The apparatus can keep high energy electrons from the surface of a wafer thereby to prevent the wafer from being charged negatively, and can trap the high energy electrons in the measuring system thereby to decrease errors in measuring a number of dopant atoms.
    Type: Grant
    Filed: October 29, 1986
    Date of Patent: November 8, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisanori Misawa, Hidetaro Nishimura, Takaya Tsujimaru, Shuji Kikuchi, Nobuyuki Abe, Kouichi Mori
  • Patent number: 4682204
    Abstract: A fuse element prepared from, for example, polycrystalline silicon is deposited on an insulating layer provided on the main surface of a semiconductor substrate in which an IC memory is formed. Connecting portions are integrally formed at both ends of the melting away portion of the fuse element. Each of the connecting portions has a stepped surface having stepped sections. The stepped surface is tightly contacted with a stepped surface having stepped sections formed on the insulating layer.
    Type: Grant
    Filed: December 11, 1985
    Date of Patent: July 21, 1987
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Masakazu Shiozaki, Hidetaro Nishimura
  • Patent number: 4532401
    Abstract: An apparatus for cutting a faulty spot or area of a predetermined wiring pattern by radiating a laser beam and which includes a reset table in which a wafer chip is fixed in place on a support table. A radiating device is disposed above the rest table to permit the laser beam to be directed at the wiring pattern. A positioning device is connected to the radiating device to position the laser beam. Between the radiating device and the support table a cover is disposed to define a hermetically-sealed space including the wafer chip. A hole of the cover is coupled to a vacuum pump. After the space is placed in a vacuum the laser beam is radiated toward the wiring pattern to permit the portion of the wiring pattern to be cut.
    Type: Grant
    Filed: March 30, 1983
    Date of Patent: July 30, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Masakazu Shiozaki, Hidetaro Nishimura
  • Patent number: 4462150
    Abstract: A method of manufacturing semiconductor devices is disclosed. In the method, a redundancy circuit is formed by forming circuit elements making up an integrated circuit on a semiconductor substrate and a spare element connected to the circuit element through an electrically non-active region. Then, an impurity region is formed in the non-active region by introducing impurity and is electrically selectively activated with laser irradiation, whereby the circuit elements and the spare element are interconnected electrically.
    Type: Grant
    Filed: September 16, 1982
    Date of Patent: July 31, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Hidetaro Nishimura, Hiroshi Nozawa