Patents by Inventor Hidetatsu Nakamura
Hidetatsu Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11869814Abstract: Types, sizes, and locations of crystal defects of an epitaxial layer of a semiconductor wafer containing silicon carbide are detected. Next, a predetermined device element structure is formed and based on location information of the crystal defects of the semiconductor wafer, semiconductor chips free of crystal defects and semiconductor chips containing only extended defects (Frank dislocations, carrot defects) are identified as conforming product candidates among individual semiconductor chips cut from the semiconductor wafer while semiconductor chips containing foreign particle defects and triangular defects are removed as non-conforming chips. Next, electrical characteristics of all the semiconductor chips that are conforming product candidates are checked. Next, based on a conforming product standard obtained in advance, a standard judgment is performed for all the semiconductor chips that are conforming product candidates, whereby semiconductor chips that are conforming products are identified.Type: GrantFiled: February 25, 2022Date of Patent: January 9, 2024Assignee: FUJI ELECTRIC CO., LTD.Inventor: Hidetatsu Nakamura
-
Patent number: 11774811Abstract: The purpose of the present invention is to prevent an overhang in a through hole in the display area when through holes in the organic passivation film in the display area and in the terminal area are simultaneously formed. The structure to realize this purpose is as follows: the terminal area having a lead wire, formed from a first metal, and extending to the display area, a first insulating film covering the lead wire, a second metal formed on the first insulating film, and a third metal formed on the surface of the second metal, wherein the first insulating film has a first through hole and a second through hole, the second metal has a first portion that connects with the lead wire via the first through hole, the second metal has a second portion that overlaps the second through hole, the second portion is separated from the first portion.Type: GrantFiled: October 20, 2020Date of Patent: October 3, 2023Assignee: Japan Display Inc.Inventors: Hidetatsu Nakamura, Yasuhiro Kanaya, Gen Koide, Hiroyuki Abe
-
Publication number: 20220367294Abstract: A method of manufacturing a silicon carbide semiconductor device. The method includes providing a starting substrate containing silicon carbide, epitaxially growing an epitaxial layer on the starting substrate to thereby form a semiconductor wafer, forming a plurality of scribe lines at a surface of the semiconductor wafer to delineate a plurality of chip regions, forming a mark in the epitaxial layer, the mark being formed in a marking region that is outside the scribe lines, inspecting the epitaxial layer for a crystal defect, forming a device element structure in at least one of the plurality of chip regions, dicing the semiconductor wafer into a plurality of individual semiconductor chips along the plurality of scribe lines, and identifying, as a conforming product candidate, one of the plurality of semiconductor chips that is free of the crystal defect detected during the inspecting.Type: ApplicationFiled: March 25, 2022Publication date: November 17, 2022Applicant: FUJI ELECTRIC CO., LTD.Inventors: Hidetatsu NAKAMURA, Keiji OKUMURA, Yoshikuni FUJIMOTO
-
Publication number: 20220367274Abstract: A method of manufacturing a silicon carbide semiconductor device. The method includes epitaxially growing an epitaxial layer on a starting substrate to form a semiconductor wafer, forming a plurality of scribe lines, including a first scribe line, in the epitaxial layer, forming a mark in the first scribe line, inspecting the epitaxial layer for a crystal defect using crystal defect inspection equipment, which recognizes the first scribe line as being a second scribe line, forming a device element structure in the semiconductor wafer, dicing the semiconductor wafer into semiconductor chips along the scribe lines, and identifying, as a conforming product candidate, one of the semiconductor chips that is free of the crystal defect detected during the inspecting. A distance between an edge of the second scribe line and an edge of the mark, when the first and second scribe lines are aligned, is in a range from 10 ?m to 25 ?m.Type: ApplicationFiled: March 29, 2022Publication date: November 17, 2022Applicant: FUJI ELECTRIC CO., LTD.Inventors: Hidetatsu NAKAMURA, Keiji OKUMURA, Yoshikuni FUJIMOTO
-
Publication number: 20220336296Abstract: Types, sizes, and locations of crystal defects of an epitaxial layer of a semiconductor wafer containing silicon carbide are detected. Next, a predetermined device element structure is formed and based on location information of the crystal defects of the semiconductor wafer, semiconductor chips free of crystal defects and semiconductor chips containing only extended defects (Frank dislocations, carrot defects) are identified as conforming product candidates among individual semiconductor chips cut from the semiconductor wafer while semiconductor chips containing foreign particle defects and triangular defects are removed as non-conforming chips. Next, electrical characteristics of all the semiconductor chips that are conforming product candidates are checked. Next, based on a conforming product standard obtained in advance, a standard judgment is performed for all the semiconductor chips that are conforming product candidates, whereby semiconductor chips that are conforming products are identified.Type: ApplicationFiled: February 25, 2022Publication date: October 20, 2022Applicant: FUJI ELECTRIC CO., LTD.Inventor: Hidetatsu NAKAMURA
-
Publication number: 20210036031Abstract: The purpose of the present invention is to prevent an overhang in a through hole in the display area when through holes in the organic passivation film in the display area and in the terminal area are simultaneously formed. The structure to realize this purpose is as follows: the terminal area having a lead wire, formed from a first metal, and extending to the display area, a first insulating film covering the lead wire, a second metal formed on the first insulating film, and a third metal formed on the surface of the second metal, wherein the first insulating film has a first through hole and a second through hole, the second metal has a first portion that connects with the lead wire via the first through hole, the second metal has a second portion that overlaps the second through hole, the second portion is separated from the first portion.Type: ApplicationFiled: October 20, 2020Publication date: February 4, 2021Inventors: Hidetatsu NAKAMURA, Yasuhiro KANAYA, Gen KOIDE, Hiroyuki ABE
-
Patent number: 10288959Abstract: A terminal structure that keeps the resistance of its connecting portion small and secures mechanical reliability is to be achieved. A display device includes a display region and a terminal region. A terminal formed in the terminal region is formed with a terminal metal, a first oxide conductive film covering the end portion of the terminal metal, and a second oxide conductive film covering the first oxide conductive film and the terminal metal. The first oxide conductive film has an opening in the center part of the terminal.Type: GrantFiled: August 4, 2017Date of Patent: May 14, 2019Assignee: Japan Display Inc.Inventors: Motoharu Miyamoto, Hidetatsu Nakamura, Yasuhiro Kanaya, Yasushi Nakano, Yasuhito Aruga
-
Publication number: 20180321563Abstract: According to one embodiment, a display device includes a first basement, a second basement having a first hole, a first conducive layer located between the first and the second basements, a sealant located between the first conductive layer and the second basement and having a second hole which is continuous with the first hole, an organic insulating layer located between the first conductive layer and the sealant and having a third hole which is continuous with the second hole, a second conductive layer located on a surface of the second basement, and a connecting material electrically connecting the first conductive layer and the second conductive layer via the first hole to third hole.Type: ApplicationFiled: April 13, 2018Publication date: November 8, 2018Applicant: Japan Display Inc.Inventors: Hidetatsu NAKAMURA, Gen Koide
-
Patent number: 10108056Abstract: A pixel electrode is configured of one comb tooth portion and a contact portion whose width is widened from the end portion of the comb tooth portion in a first direction that is the extending direction of a scanning line. The width of the contact portion is not expanded in a direction opposite to the first direction, and the production of a domain is prevented. A picture signal line is bent in the direction in which the width of the contact portion of the pixel electrode is widened, so that the comb tooth portion of the pixel electrode can be disposed in the center between the picture signal lines, and the width of the contact portion can be formed in a sufficient width in the direction in which the picture signal line is bent. Thus, the contact margin of the pixel electrode can be provided.Type: GrantFiled: July 17, 2017Date of Patent: October 23, 2018Assignee: Japan Display Inc.Inventors: Hidetatsu Nakamura, Osamu Itou, Takeshi Sakai
-
Publication number: 20180046012Abstract: A terminal structure that keeps the resistance of its connecting portion small and secures mechanical reliability is to be achieved. A display device includes a display region and a terminal region. A terminal formed in the terminal region is formed with a terminal metal, a first oxide conductive film covering the end portion of the terminal metal, and a second oxide conductive film covering the first oxide conductive film and the terminal metal. The first oxide conductive film has an opening in the center part of the terminal.Type: ApplicationFiled: August 4, 2017Publication date: February 15, 2018Inventors: Motoharu MIYAMOTO, Hidetatsu NAKAMURA, Yasuhiro KANAYA, Yasushi NAKANO, Yasuhito ARUGA
-
Publication number: 20170315413Abstract: A pixel electrode is configured of one comb tooth portion and a contact portion whose width is widened from the end portion of the comb tooth portion in a first direction that is the extending direction of a scanning line. The width of the contact portion is not expanded in a direction opposite to the first direction, and the production of a domain is prevented. A picture signal line is bent in the direction in which the width of the contact portion of the pixel electrode is widened, so that the comb tooth portion of the pixel electrode can be disposed in the center between the picture signal lines, and the width of the contact portion can be formed in a sufficient width in the direction in which the picture signal line is bent. Thus, the contact margin of the pixel electrode can be provided.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Inventors: Hidetatsu NAKAMURA, Osamu ITOU, Takeshi SAKAI
-
Patent number: 9740062Abstract: A pixel electrode is configured of one comb tooth portion and a contact portion whose width is widened from the end portion of the comb tooth portion in a first direction that is the extending direction of a scanning line. The width of the contact portion is not expanded in a direction opposite to the first direction, and the production of a domain is prevented. A picture signal line is bent in the direction in which the width of the contact portion of the pixel electrode is widened, so that the comb tooth portion of the pixel electrode can be disposed in the center between the picture signal lines, and the width of the contact portion can be formed in a sufficient width in the direction in which the picture signal line is bent. Thus, the contact margin of the pixel electrode can be provided.Type: GrantFiled: May 28, 2015Date of Patent: August 22, 2017Assignee: Japan Display Inc.Inventors: Hidetatsu Nakamura, Osamu Itou, Takeshi Sakai
-
Patent number: 9577095Abstract: A semiconductor device includes a MISFET. The semiconductor device also includes a silicon nitride film 12 and a silicon nitride film 10 arranged on the silicon nitride film 12. The silicon nitride film 12 covers at least a portion of an upper part of a source/drain 8 of the MISFET and has a film thickness thinner than a height of a gate electrode 4. The source/drain 8 includes nickel silicide 9 on its boundary to the silicon nitride film 10. The silicon nitride film 10 is a stressed film. A tight adhering property between the silicon nitride film 12 and the surface of the source/drain 8 and that between the silicon nitride film 12 and the silicon nitride film 10 are rendered higher than a tight adhering property which would prevail when the silicon nitride film 10 be made to adhere tightly to the source/drain 8.Type: GrantFiled: April 30, 2015Date of Patent: February 21, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuya Uejima, Hidetatsu Nakamura, Akihito Sakakidani, Eiichirou Watanabe
-
Publication number: 20150346566Abstract: A pixel electrode is configured of one comb tooth portion and a contact portion whose width is widened from the end portion of the comb tooth portion in a first direction that is the extending direction of a scanning line. The width of the contact portion is not expanded in a direction opposite to the first direction, and the production of a domain is prevented. A picture signal line is bent in the direction in which the width of the contact portion of the pixel electrode is widened, so that the comb tooth portion of the pixel electrode can be disposed in the center between the picture signal lines, and the width of the contact portion can be formed in a sufficient width in the direction in which the picture signal line is bent. Thus, the contact margin of the pixel electrode can be provided.Type: ApplicationFiled: May 28, 2015Publication date: December 3, 2015Inventors: Hidetatsu NAKAMURA, Osamu ITOU, Takeshi SAKAI
-
Publication number: 20150236156Abstract: A semiconductor device includes a MISFET. The semiconductor device also includes a silicon nitride film 12 and a silicon nitride film 10 arranged on the silicon nitride film 12. The silicon nitride film 12 covers at least a portion of an upper part of a source/drain 8 of the MISFET and has a film thickness thinner than a height of a gate electrode 4. The source/drain 8 includes nickel silicide 9 on its boundary to the silicon nitride film 10. The silicon nitride film 10 is a stressed film. A tight adhering property between the silicon nitride film 12 and the surface of the source/drain 8 and that between the silicon nitride film 12 and the silicon nitride film 10 are rendered higher than a tight adhering property which would prevail when the silicon nitride film 10 be made to adhere tightly to the source/drain 8.Type: ApplicationFiled: April 30, 2015Publication date: August 20, 2015Inventors: Kazuya UEJIMA, Hidetatsu NAKAMURA, Akihito SAKAKIDANI, Eiichirou WATANABE
-
Publication number: 20120181587Abstract: A semiconductor device includes a MISFET. The semiconductor device also includes a silicon nitride film 12 and a silicon nitride film 10 arranged on the silicon nitride film 12. The silicon nitride film 12 covers at least a portion of an upper part of a source/drain 8 of the MISFET and has a film thickness thinner than a height of a gate electrode 4. The source/drain 8 includes nickel silicide 9 on its boundary to the silicon nitride film 10. The silicon nitride film 10 is a stressed film. A tight adhering property between the silicon nitride film 12 and the surface of the source/drain 8 and that between the silicon nitride film 12 and the silicon nitride film 10 are rendered higher than a tight adhering property which would prevail when the silicon nitride film 10 be made to adhere tightly to the source/drain 8.Type: ApplicationFiled: February 29, 2012Publication date: July 19, 2012Applicants: RENESAS ELECTRONICS CORPORATION, NEC CORPORATIONInventors: Kazuya UEJIMA, Hidetatsu NAKAMURA, Akihito SAKAKIDANI, Eiichirou WATANABE
-
Publication number: 20100224941Abstract: A semiconductor device includes a MISFET. The semiconductor device also includes a silicon nitride film 12 and a silicon nitride film 10 arranged on the silicon nitride film 12. The silicon nitride film 12 covers at least a portion of an upper part of a source/drain 8 of the MISFET and has a film thickness thinner than a height of a gate electrode 4. The source/drain 8 includes nickel suicide 9 on its boundary to the silicon nitride film 10. The silicon nitride film 10 is a stressed film. A tight adhering property between the silicon nitride film 12 and the surface of the source/drain 8 and that between the silicon nitride film 12 and the silicon nitride film 10 are rendered higher than a tight adhering property which would prevail when the silicon nitride film 10 be made to adhere tightly to the source/drain 8.Type: ApplicationFiled: June 5, 2007Publication date: September 9, 2010Applicants: NEC CORPORATION, NEC ELECTRONICS CORPORATIONInventors: Kazuya Uejima, Hidetatsu Nakamura, Akihito Sakakidani, Eiichirou Watanabe
-
Publication number: 20100019325Abstract: In a semiconductor device, a contact stopper film having a stress is provided to cover a group of MISFETs arranged in a gate-length direction. The stopper film has an extension part that extends by a length L=1 ?m or more toward the outside of the gate electrode of the MISFET located the endmost part of the MISFET group.Type: ApplicationFiled: March 3, 2008Publication date: January 28, 2010Inventors: Hidetatsu Nakamura, Kazuya Uejima
-
Publication number: 20090045466Abstract: There are accomplished nMOSFET and pMOSFET both having high mobility, by optimizing stress and location of a film existing around a gate electrode such that high stress acts on a channel. In nMOSFET, a first film having compressive stress is formed on a gate electrode, and a second film having tensile stress is formed covering a gate electrode, a sidewall spacer of a gate electrode, and source/drain regions therewith. In pMOSFET, a film having tensile stress is formed on the gate electrode in place of the first film, and a film having compressive stress is formed in place of the second film.Type: ApplicationFiled: September 13, 2006Publication date: February 19, 2009Applicant: NEC CORPORATIONInventor: Hidetatsu Nakamura