Abstract: Described herein is a technique capable of acquiring, monitoring, and recording the progress of the reaction between a substrate and a reactive gas contained in a process gas in a process chamber during the processing of the substrate. According to the technique, there is provided a substrate processing apparatus including: a process chamber accommodating a substrate; a process gas supply system configured to supply a process gas into the process chamber via a process gas supply pipe; an exhaust pipe configured to exhaust an inner atmosphere of the process chamber; a first gas concentration sensor configured to detect a first concentration of a reactive gas contained in the process gas in the process gas supply pipe; and a second gas concentration sensor configured to detect a second concentration of the reactive gas contained in an exhaust gas in the exhaust pipe.

Abstract: A memory system has a memory cell array having a plurality of strings, the plurality of strings each having a plurality of memory cells connected in series, and a controller configured to perform control of transferring charges to be stored in the plurality of memory cells in the string or transferring charges according to stored data, between potential wells of channels in the plurality of memory cells.

Abstract: A semiconductor device includes a first conductive layer extending along a first direction, a semiconductor layer extending along a second direction crossing the first direction, penetrating the first conductive layer, and including an oxide semiconductor, a first insulating layer between the first conductive layer and the semiconductor layer, a second conductive layer provided on one side of the semiconductor layer in the second direction and electrically connected thereto, a third conductive layer provided on the other side of the semiconductor layer in the second direction and electrically connected thereto, an electric conductor extending from the third conductive layer toward the second conductive layer along the semiconductor layer, and a charge storage film between the semiconductor layer and the electric conductor.

Abstract: A memory system has a memory cell array having a plurality of strings, the plurality of strings each having a plurality of memory cells connected in series, and a controller configured to perform control of transferring charges to be stored in the plurality of memory cells in the string or transferring charges according to stored data, between potential wells of channels in the plurality of memory cells.

Abstract: An example semiconductor device includes: n conductive layers including first to nth conductive layers stacked in a first direction; a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type closer to the nth conductive layer than the first semiconductor region; a semiconductor layer provided between the first semiconductor region and the second semiconductor region, extending in the first direction, penetrating the n conductive layers, and having an impurity concentration lower than a first conductive impurity concentration of the first region and a second conductive impurity concentration of the second region; n charge storage regions including first to nth charge storage regions provided between the n conductive layers and the semiconductor layer, and a control circuit that controls a voltage applied to the n conductive layers to always prevent charges from being stored in at least one of the n charge storage regions.

Abstract: A semiconductor memory device includes a plurality of memory cells, a plurality of word lines connected to the plurality of memory cells, respectively, and a row control circuit. The row control circuit is configured to apply a program voltage to a first word line among the word lines while stepping up a value of the program voltage; apply a first pass voltage to a second word line among the word lines different from the first word line when applying the program voltage having a voltage value equal to or greater than a predetermined voltage value to the first word line; and apply a second pass voltage having a voltage value higher than the first pass voltage to the second word line when applying the program voltage having a voltage value less than the predetermined voltage value to the first word line.

Abstract: An example semiconductor device includes: n conductive layers including first to nth conductive layers stacked in a first direction; a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type closer to the nth conductive layer than the first semiconductor region; a semiconductor layer provided between the first semiconductor region and the second semiconductor region, extending in the first direction, penetrating the n conductive layers, and having an impurity concentration lower than a first conductive impurity concentration of the first region and a second conductive impurity concentration of the second region; n charge storage regions including first to nth charge storage regions provided between the n conductive layers and the semiconductor layer, and a control circuit that controls a voltage applied to the n conductive layers to always prevent charges from being stored in at least one of the n charge storage regions.

Abstract: A semiconductor memory device includes a plurality of memory cells, a plurality of word lines connected to the plurality of memory cells, respectively, and a row control circuit. The row control circuit is configured to apply a program voltage to a first word line among the word lines while stepping up a value of the program voltage; apply a first pass voltage to a second word line among the word lines different from the first word line when applying the program voltage having a voltage value equal to or greater than a predetermined voltage value to the first word line; and apply a second pass voltage having a voltage value higher than the first pass voltage to the second word line when applying the program voltage having a voltage value less than the predetermined voltage value to the first word line.

Abstract: In a write operation to memory cells, the control unit is operative to, when a threshold voltage to be provided to a selected memory cell is not less than a reference value, apply a program voltage to a word line corresponding to a selected memory cell, and cause a voltage applied to a first word line corresponding to a first non-selected memory cell positioned between the first end and the selected memory cell to be higher than a voltage applied to a second word line corresponding to a second non-selected memory cell positioned between the second end and the selected memory cell.

Abstract: According to an embodiment, a non-volatile semiconductor memory device comprises a NAND cell unit, a bit-line, a source-line, word-lines and a control circuit. The NAND cell unit comprises memory cells connected in series. The bit-line is connected to an end of the NAND cell unit. The source-line is connected to the other end of the NAND cell unit. The word-lines are connected to respective control gates of the memory cells. The control circuit applies, to a non-selected word-line on the bit-line side of a predetermined boundary in the NAND cell unit, a first read-pass voltage turning on the memory cell regardless of the cell data. The control circuit applies, to a non-selected word-line on the source-line side of the predetermined boundary, a second read-pass voltage less than the first read-pass voltage. The control circuit provides a read bit-line voltage between the bit-line and the source-line.

Abstract: A non-volatile semiconductor memory device according to one aspect of an embodiment of the present invention includes: a semiconductor substrate; an element region; a plurality of memory cell transistors which each include a control gate electrode; and programming means for programming data to a programming target memory cell transistor by applying a programming voltage to the programming target memory cell transistor. Moreover, the programming means applies a programming voltage incremented stepwise from an initial programming voltage, to the programming target memory cell transistor while applying a constant initial intermediate voltage to memory cell transistors adjacent to the programming target memory cell transistor.

Abstract: According to one embodiment, a NAND nonvolatile semiconductor memory device comprises memory cell transistors and a write circuit. The memory cell transistors are arranged in a matrix in a column direction and in a row direction. Each of the memory cell transistors comprises a charge accumulation layer and a control gate electrode configured to control the charge accumulation state of the charge accumulation layer. The write circuit carries out write on the memory cell transistors. The memory cell transistors arranged in the same line include first memory cell transistors and second memory cell transistors that are smaller than the first memory cell transistors in the column direction. The write circuit carries out write on a predetermined first memory cell transistor and then on another first memory cell transistor. After the write on the another first memory cell transistor, the write circuit carries out write on the second memory cell transistor.

Abstract: A non-volatile semiconductor memory device according to one aspect of an embodiment of the present invention includes: a semiconductor substrate; an element region; a plurality of memory cell transistors which each include a control gate electrode; and programming means for programming data to a programming target memory cell transistor by applying a programming voltage to the programming target memory cell transistor. Moreover, the programming means applies a programming voltage incremented stepwise from an initial programming voltage, to the programming target memory cell transistor while applying a constant initial intermediate voltage to memory cell transistors adjacent to the programming target memory cell transistor.

Abstract: According to one embodiment, a NAND nonvolatile semiconductor memory device comprises memory cell transistors and a write circuit. The memory cell transistors are arranged in a matrix in a column direction and in a row direction. Each of the memory cell transistors comprises a charge accumulation layer and a control gate electrode configured to control the charge accumulation state of the charge accumulation layer. The write circuit carries out write on the memory cell transistors. The memory cell transistors arranged in the same line include first memory cell transistors and second memory cell transistors that are smaller than the first memory cell transistors in the column direction. The write circuit carries out write on a predetermined first memory cell transistor and then on another first memory cell transistor. After the write on the another first memory cell transistor, the write circuit carries out write on the second memory cell transistor.

Abstract: A non volatile semiconductor memory device includes: a semiconductor substrate comprising element regions; gate structures each comprising a first gate insulation film, a charge storage layer, a second gate insulation film, and a control gate; element isolation insulation films defining the element regions and electrically isolating the element regions; impurity diffusion layers in the element regions; a third gate insulation film of a first insulation material located between the gate structures; and a fourth gate insulation film of a second insulation material which is different from the first insulation material configured to be in contact with side walls of the gate structures. A bottom face of the fourth gate insulation film is located so as to be remote from a surface of the semiconductor substrate by a distance equal to at least half of a height of the charge storage layer.