Abstract: A search circuit includes a search table including a plurality of entry data, a search processing unit receiving a search key and performing a binary search operation for the search table. Each of the plurality of entry data includes a search data, a prefix length data and a search result data. The search processing unit reads one of the plurality of entry data from the search table according to a binary search operation, specifies a search target range based on the search data and the prefix length data in the read entry data, determines whether the search key is included in the search target range, and outputs the search result data of the read entry data based on a determination result.

Abstract: A search circuit includes a search table including a plurality of entry data, a search processing unit receiving a search key and performing a binary search operation for the search table. Each of the plurality of entry data includes a search data, a prefix length data and a search result data. The search processing unit reads one of the plurality of entry data from the search table according to a binary search operation, specifies a search target range based on the search data and the prefix length data in the read entry data, determines whether the search key is included in the search target range, and outputs the search result data of the read entry data based on a determination result.

Abstract: A search circuit capable of efficiently executing a search process while suppressing an increase in memory chips is provided. The search circuit includes a first memory, a second memory and a processor which executes a binary search with the first and the second memory. The plurality of entry data are divided into a two search stage groups according to a reading order position of a binary search and are stored in the first and the second memory for each groups. The second memory includes a plurality of memory banks provided according to the number of search stages of the corresponding group. The memory banks each stores entry data for each search stages.

Abstract: Provided is a search memory capable of suppressing an increase in the area of a chip and an increase in the amount of current consumption. The search memory includes an input control section, N search units, and N first selectors. The input control section receives N (N: two or more) search data that are parallelly inputted. The N first selectors are respectively disposed in association with the N search units to select two search data from the N search data. The search units each include multiple search blocks and M second selectors. The M second selectors select one of two search data selected by the first selectors. For at least one of the N search units, allocation is performed so that two types out of N types of entry data respectively associated with the N search data are respectively stored in the search blocks.

Abstract: A technique for reducing power consumption of a content addressable memory (CAM) system is provided. In a CAM system, an equalizer circuit is coupled to a border portion between a plurality of match line parts generated by dividing each match line corresponding to a piece of entry data, and a precharge circuit precharges each of the match line parts collectively corresponding to a piece of entry data to voltage VDD or VSS. When comparing the entry data and search data, the equalizer circuit couples, in accordance with a control signal, the match line parts after the match line parts are precharged by the precharge circuit. In an equalization period, search operation through the search line is started. A search transistor for comparing search data and entry data includes an NMOS search transistor.

Abstract: Provided is a search memory capable of suppressing an increase in the area of a chip and an increase in the amount of current consumption. The search memory includes an input control section, N search units, and N first selectors. The input control section receives N (N: two or more) search data that are parallelly inputted. The N first selectors are respectively disposed in association with the N search units to select two search data from the N search data. The search units each include multiple search blocks and M second selectors. The M second selectors select one of two search data selected by the first selectors. For at least one of the N search units, allocation is performed so that two types out of N types of entry data respectively associated with the N search data are respectively stored in the search blocks.

Abstract: A technique for reducing power consumption of a content addressable memory (CAM) system is provided. In a CAM system, an equalizer circuit is coupled to a border portion between a plurality of match line parts generated by dividing each match line corresponding to a piece of entry data, and a precharge circuit precharges each of the match line parts collectively corresponding to a piece of entry data to voltage VDD or VSS. When comparing the entry data and search data, the equalizer circuit couples, in accordance with a control signal, the match line parts after the match line parts are precharged by the precharge circuit. In an equalization period, search operation through the search line is started. A search transistor for comparing search data and entry data includes an NMOS search transistor.

Abstract: A technique for reducing power consumption of a content addressable memory (CAM) system is provided. In a CAM system, an equalizer circuit is coupled to a border portion between a plurality of match line parts generated by dividing each match line corresponding to a piece of entry data, and a precharge circuit precharges each of the match line parts collectively corresponding to a piece of entry data to voltage VDD or VSS. When comparing the entry data and search data, the equalizer circuit couples, in accordance with a control signal, the match line parts after the match line parts are precharged by the precharge circuit. In an equalization period, search operation through the search line is started. A search transistor for comparing search data and entry data includes an NMOS search transistor.

Abstract: A technique for reducing power consumption of a content addressable memory (CAM) system is provided. In a CAM system, an equalizer circuit is coupled to a border portion between a plurality of match line parts generated by dividing each match line corresponding to a piece of entry data, and a precharge circuit precharges each of the match line parts collectively corresponding to a piece of entry data to voltage VDD or VSS. When comparing the entry data and search data, the equalizer circuit couples, in accordance with a control signal, the match line parts after the match line parts are precharged by the precharge circuit. In an equalization period, search operation through the search line is started. A search transistor for comparing search data and entry data includes an NMOS search transistor.

Abstract: A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search data sequence. A second input pin receives an input of a search data sequence arbitrarily designating a content-addressable-memory sub-array. Each of the content-addressable-memory sub-arrays includes an activation control unit that controls activation of the content-addressable-memory sub-arrays based on the search data sequence.

Abstract: A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search data sequence. A second input pin receives an input of a search data sequence arbitrarily designating a content-addressable-memory sub-array. Each of the content-addressable-memory sub-arrays includes an activation control unit that controls activation of the content-addressable-memory sub-arrays based on the search data sequence.

Abstract: A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search data sequence. A second input pin receives an input of a search data sequence arbitrarily designating a content-addressable-memory sub-array. Each of the content-addressable-memory sub-arrays includes an activation control unit that controls activation of the content-addressable-memory sub-arrays based on the search data sequence.

Abstract: A pellicle comprises a pellicle film and a pellicle frame for supporting the pellicle film, wherein the pellicle film is adhered to the pellicle frame through an adhesive layer comprising a fluorine-containing polymer and a substance resulting from curing of an ultraviolet-curing fluorine-containing monomer. A producing method of a pellicle including a pellicle film and a pellicle frame for supporting the pellicle film, comprises a step of adhering the pellicle film to the pellicle frame through an adhesive comprising a fluorine-containing polymer and an ultraviolet-curing fluorine-containing monomer.

Abstract: A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search data sequence. A second input pin receives an input of a search data sequence arbitrarily designating a content-addressable-memory sub-array. Each of the content-addressable-memory sub-arrays includes an activation control unit that controls activation of the content-addressable-memory sub-arrays based on the search data sequence.

Abstract: A shift information latch circuit includes a plurality of latch portions provided corresponding to memory cell rows, respectively, and a fuse circuit transmitting fuse data produced corresponding to an address of a faulty memory cell row. The plurality of latch portion successively receive fuse data, and each transmit a shift control signal instructing a shift operation. In response to this shift control signal, a row decoder and a match line amplifier execute a shift operation for repairing the faulty memory cell row. In this structure, a decoder circuit decoding the address of the faulty memory cell row is not arranged so that a whole area of the circuits executing the shift operation is reduced, and the shift operation can be easily executed.

Abstract: A shift information latch circuit includes a plurality of latch portions provided corresponding to memory cell rows, respectively, and a fuse circuit transmitting fuse data produced corresponding to an address of a faulty memory cell row. The plurality of latch portion successively receive fuse data, and each transmit a shift control signal instructing a shift operation. In response to this shift control signal, a row decoder and a match line amplifier execute a shift operation for repairing the faulty memory cell row. In this structure, a decoder circuit decoding the address of the faulty memory cell row is not arranged so that a whole area of the circuits executing the shift operation is reduced, and the shift operation can be easily executed.

Abstract: A dual port DRAM cell of a memory cell array circuit (110) has two ports, each connected to a bit line. The bit line is of open-bit-line configuration and is connected to a sense amplifier. An access circuit (150A) and an access circuit (150B) access to memory cells via one port and the other port, respectively. When the access circuit (150A) accesses to the memory cell, the sense amplifier amplifies the potential of the bit line connected to the access-object cell. During this amplification period, the access circuit (150A) outputs a control signal (WLONA). The access circuit (150B) receives the control signal (WLONA) and operates so as not to change, during the amplification period, the potential of a bit line adjacent to the bit line that is in the amplification period and is used by the access circuit (150B) at the time of access.

Abstract: A pellicle comprises a pellicle film and a pellicle frame for supporting the pellicle film, wherein the pellicle film is adhered to the pellicle frame through an adhesive layer comprising a fluorine-containing polymer and a substance resulting from curing of an ultraviolet-curing fluorine-containing monomer. A producing method of a pellicle including a pellicle film and a pellicle frame for supporting the pellicle film, comprises a step of adhering the pellicle film to the pellicle frame through an adhesive comprising a fluorine-containing polymer and an ultraviolet-curing fluorine-containing monomer.

Abstract: A method for producing aryl alkyl hydroperoxides which comprises selectively oxidizing an aryl alkyl hydrocarbon having the formula: ##STR1## wherein P and Q are hydrogen or an alkyl and may be the same or different from each other; x is an integer of 1-3; and Ar is an aromatic hydrocarbon group having a valence of x, with an oxygen-containing gas in the presence of a transition metal complex which contains, as a ligand, a cyclic polyfunctional amine compound having at least three nitrogen atoms in the ring forming molecular chain or an open chain polyfunctional amine compound having at least three nitrogen atoms in the main chain of the molecule.

Abstract: A method for producing aryl alkyl hydroperoxides which comprises selectively oxidizing an aryl alkyl hydrocarbon having the formula: ##STR1## wherein P and Q are hydrogen or an alkyl and may be the same or different from each other; x is an integer of 1-3; and Ar is an aromatic hydrocarbon group having a valence of x, with an oxygen-containing gas in the presence of a transition metal complex which contains, as a ligand, a cyclic polyfunctional amine compound having at least three nitrogen atoms in the ring forming molecular chain or an open chain polyfunctional amine compound having at least three nitrogen atoms in the main chain of the molecule.