Patents by Inventor Hideto Niijima
Hideto Niijima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5928315Abstract: Apparatus method for calculating the remainder of B.sup.C modulo n at high speed with minimum hardware resources, while securing the safety of the key in a cryptographic system. The apparatus comprises circuitry including registers for executing an initial and normal cycles, cumulating and storing the calculation result of each cycle and for outputting from a least significant bit. The initial cycle of the calculation includes a step of calculating a remainder of an m-bit input modulo n and a step of holding the result of the calculation. The normal cycle of the calculation includes a step of doubling the result of the calculation, and calculating a remainder of the doubled result of the calculation modulo n and a step of holding the next result of the calculation and for repeatedly executing the normal cycle m-2 times after the first normal cycle. The calculation result of each previous normal cycle is used in each successive normal cycle.Type: GrantFiled: September 12, 1997Date of Patent: July 27, 1999Assignee: International Business Machines CorporationInventors: Yoshinao Kobayashi, Akashi Satoh, Hideto Niijima
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Patent number: 5923839Abstract: A data storage system is provided having a faster data transfer rate and reduced complexity though improved control of timing. The data storage system has a plurality of storage devices and a plurality of data buses through which data are transferred. An input/output unit interleaves a plurality of data between an interface and the plurality of data buses while transferring data. A first and a second latch unit, serially connected between the storage devices and the data bus, retain data.Type: GrantFiled: November 20, 1996Date of Patent: July 13, 1999Assignee: International Business Machines CorporationInventors: Seiji Munetoh, Hiroki Murata, Hideto Niijima, Nobuaki Takahashi
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Patent number: 5892780Abstract: The present invention provides a method and apparatus for generating parity in a data storage system. The data storage system includes two or more storage devices having data stored therein, two or more data buses through which the data is transferred, and a selector located between the storage devices and the buses which selectively connects the storage devices and the data buses by a predetermined combination. The selector further includes the capability of calculating parity operations such as an XOR operation. The selector performs the parity operations to logically combine data transferred through the selector between the data buses and the storage devices to produce parity data on the combined data transferred so as to reduce the data transfers over the data bus.Type: GrantFiled: July 15, 1997Date of Patent: April 6, 1999Assignee: International Business Machines CorporationInventors: Seiji Munetoh, Hideto Niijima, Hiroki Murata, Nobuaki Takahashi
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Patent number: 5889795Abstract: A system is provided for improving the speed for writing data in a disk array system. The disk array system includes a solid state disk storage device configured with semiconductor flash memory to sequentially store the parity for the disk array. The solid state disk storage device allows data sectors to be assigned sequentially in a cluster consisting of a set of blocks. Each block is a physical unit of erasure. Write operations for a plurality of sectors are written across the set of blocks in the cluster.Type: GrantFiled: March 10, 1997Date of Patent: March 30, 1999Assignee: International Business Machines CorporationInventors: Hideto Niijima, Nobuyuki Matsuo, Mayumi Shimada
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Patent number: 5875458Abstract: A disk storage device includes two data buses 100, 200 for data transfer. Hard disks (HDDs) 0 and 1 are permanently connected to the data buses 100, 200, and hard disks 2 and 3 are selectively connectable to either of the data buses. When a microcontroller (MCU) 32 outputs a specified signal to a data path controller (DPC) 10 in response to a command from a host, multiplexers 20, 22 connect the selectively connectable hard disks 2 and 3 to one of the data buses. When data is written to or read from the hard disks, the write or read can be performed quickly with fewer data buses and a simple device configuration. A parity data generator (PGEN) 24 is connected to both of the buses, receiving new data via one bus and writing new parity data via the other bus.Type: GrantFiled: April 28, 1997Date of Patent: February 23, 1999Assignee: International Business Machines CorporationInventors: Hideto Niijima, Seiji Munetoh, Hiroki Murata, Nobuaki Takahashi
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Patent number: 5844910Abstract: An array of memory cells is physically divided into a data area and a tag area so that respective parts of the two areas share a word line but can be separately erased en bloc. The data area and tag area sharing one word line constitute a single logical unit. In the logical unit, the tag area stores location information for defective memory cells in the corresponding data area. On the basis of this information, the system avoids the use of the defective memory cells. The defective memory cell information is programmed in a test step performed after chip manufacture and, at the same time, ECCs are generated for the defective memory cell information and written to the tag area. Furthermore, the system is informed of the invalidity of the data area that shares a word line with a tag area by writing predetermined data to the tag area. Even when the data area is erased en bloc, the tag area is not erased and the defective memory cell information is retained there.Type: GrantFiled: August 7, 1996Date of Patent: December 1, 1998Assignee: International Business Machines CorporationInventors: Hideto Niijima, Takashi Toyooka, Akashi Satoh, Yoshinori Sakaue
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Patent number: 5799140Abstract: A method and system are provided for improving the speed for writing data in a disk array system (RAID). Disks are divided into the ones for reading old data and the other ones for writing new data. An external semiconductor storage device is used as a parity device which significantly enhances performance in writing.A disk array system is used for storing data for which a parity group comprises N data units stored in sectors of N magnetic disk drives with parity stored in the parity device. At least N+1 data-storing magnetic disk drives are provided, where sectors of at least one magnetic disk drive are used as redundant sectors.Type: GrantFiled: March 10, 1997Date of Patent: August 25, 1998Assignee: International Business Machines CorporationInventors: Hideto Niijima, Nobuyuki Matsuo, Mayumi Shimada
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Patent number: 5787493Abstract: With the present invention, the page table of the program code non-continuously placed in an external storage device using randomly accessible and rewritable memory is built into an executable sequence in a virtual address space of the CPU according to the execution order. By referring to the address translation tables, including the page table, the system is able to read the program from the external storage device, thereby executing the program. Therefore, the program can be executed without being loaded into main memory. Furthermore, the program and data can be managed without distinction.Further, with the randomly accessible memory according to the present invention, since a sequence of real addresses of the CPU are assigned to the data area, control over the direct execution of the program can be simply achieved. Furthermore, since data and ECC parity can also be read and written sequentially, the system has good compatibility with a hard disk system.Type: GrantFiled: April 8, 1997Date of Patent: July 28, 1998Assignee: International Business Machines CorporationInventors: Hideto Niijima, Akashi Satoh
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Patent number: 5742625Abstract: An object of the present invention is to provide a data storage system and a parity generation method for the data storage system which make generation of parity easier and which are capable of performing the reconstruction of data at the time of an occurrence of failure with high efficiency and high speed.A data storage system is provided comprising a plurality of devices for storing data, a plurality of data buses for transferring the data, and a selector connected between the plurality of devices and the plurality of data buses for selectively connecting a device and a data bus using a predetermined combination, the selector including a parity operation generator.Type: GrantFiled: January 26, 1996Date of Patent: April 21, 1998Assignee: International Business Machines CorporationInventors: Seiji Munetoh, Hideto Niijima, Hiroki Murata, Nobuaki Takahashi
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Patent number: 5734816Abstract: A nonvolatile memory with flash erase capability includes a plurality of clusters each having a plurality of sectors, each of the sectors holding the attribute information for identification. A cluster information sector is placed at the top of a cluster to which it belongs. A data sector is placed in a data area which is the region other than the top of the cluster. A controller connected to the nonvolatile memory creates a cluster information copy sector when erasing a cluster, and reconstructs cluster management information from the cluster information copy sector when initializing a cluster, thereby forming a cluster information sector. Accordingly, endurance against failure such as power failure in a solid state file apparatus using the nonvolatile memory is improved.Type: GrantFiled: March 10, 1994Date of Patent: March 31, 1998Assignee: International Business Machines CorporationInventors: Hideto Niijima, Takashi Toyooka
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Patent number: 5650969Abstract: A method and system are provided for improving the speed for writing data in a disk array system (RAID). Sectors of the disks are divided into the ones for reading old data and the other ones for writing new data. An external semiconductor storage device is used as a parity device which significantly enhances performance in writing. Preferably, a disk array system is used for storing data for which a parity group comprises N data units stored in sectors of N magnetic disk drives with parity stored in the parity device. At least N+1 magnetic disk drives are provided, where sectors of at least one magnetic disk drive are used as redundant sectors.Type: GrantFiled: April 21, 1995Date of Patent: July 22, 1997Assignee: International Business Machines CorporationInventors: Hideto Niijima, Nobuyuki Matsuo, Mayumi Shimada
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Nonvolatile memory with cluster-erase flash capability and solid state file apparatus using the same
Patent number: 5598370Abstract: A nonvolatile memory-with cluster-erase flash capability. A cluster information sector is included in each of N clusters, the cluster information sector of each cluster being written with the sequence number assigned to the cluster so that no two clusters have the same sequence number. When erasing a given sector, a controller saves its sequence number prior to erasure. Then, when initializing a given erased sector, the controller sets its sequence number to a value greater than the current maximum sequence number. The controller writes user data to sectors other than the cluster information sector for the cluster thus initialized according to their address sequence. Accordingly, an invalid sector can be distinguished from a valid sector without using an overwrite approach.Type: GrantFiled: April 26, 1995Date of Patent: January 28, 1997Assignee: International Business Machines CorporationInventors: Hideto Niijima, Hideo Asano, Yoshinori Sakaue, Takashi Toyooka -
Patent number: 5546402Abstract: An array of memory cells is physically divided into a data area and a tag area so that respective parts of the two areas share a word line but can be separately erased en bloc. The data area and tag area sharing one word line constitute a single logical unit. In the logical unit, the tag area stores location information for defective memory cells in the corresponding data area. On the basis of this information, the system avoids the use of the defective memory cells. The defective memory cell information is programmed in a test step performed after chip manufacture and, at the same time, ECCs are generated for the defective memory cell information and written to the tag area. Furthermore, the system is informed of the invalidity of the data area that shares a word line with a tag area by writing predetermined data to the tag area. Even when the data area is erased en bloc, the tag area is not erased and the defective memory cell information is retained there.Type: GrantFiled: June 7, 1995Date of Patent: August 13, 1996Assignee: International Business Machines CorporationInventors: Hideto Niijima, Takashi Toyooka, Akashi Satoh, Yoshinori Sakaue
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Patent number: 5524230Abstract: To provide an external storage system using a semiconductor memory in which the data reading and writing between the host CPU can be processed faster than the conventional magnetic disk, and only a particular sector is not frequently written and erased so that the whole memory is effectively used over a long period of time. An address control scheme was introduced in which flexibility is given to the address relation between the host CPU and the external storage and the physical address of the semiconductor memory is not one-sidedly determined by the logical address possessed by the command of the host CPU. Command processing section 34 always prepares memory blocks and sectors for writing or erasing and copying in preparation for the command processing of the host CPU, and records and holds the correspondence relation between the physical address of the selected memory block 32i or sector and the command of the host CPU in address conversion table 36.Type: GrantFiled: March 27, 1995Date of Patent: June 4, 1996Assignee: International Business Machines IncorporatedInventors: Yoshinori Sakaue, Hideto Niijima
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Patent number: 5509018Abstract: An array of memory cells is physically divided into a data area and a tag area so that respective parts of the two areas share a word line but can be separately erased en bloc. The data area and tag area sharing one word line constitute a single logical unit. In the logical unit, the tag area stores location information for defective memory cells in the corresponding data area. On the basis of this information, the system avoids the use of the defective memory cells. The defective memory cell information is programmed in a test step performed after chip manufacture and, at the same time, ECCs are generated for the defective memory cell information and written to the tag area. Furthermore, the system is informed of the validity of the data area that shares a word line with a tag area by writing predetermined data to the tag area. Even when the data area is erased en bloc, the tag area is not erased and the defective memory cell information is retained there.Type: GrantFiled: September 10, 1993Date of Patent: April 16, 1996Assignee: International Business Machines CorporationInventors: Hideto Niijima, Takashi Toyooka, Akashi Satoh, Yoshinori Sakaue
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Nonvolatile memory with cluster-erase flash capability and solid state file apparatus using the same
Patent number: 5457658Abstract: A nonvolatile memory with cluster-erase flash capability. A cluster information sector is included in each of N clusters, the cluster information sector of each cluster being written with the sequence number assigned to the cluster so that no two clusters have the same sequence number. When erasing a given sector, a controller saves its sequence number prior to erasure. Then, when initializing a given erased sector, the controller sets its sequence number to a value greater than the current maximum sequence number. The controller writes user data to sectors other than the cluster information sector for the cluster thus initialized according to their address sequence. Accordingly, an invalid sector can be distinguished from a valid sector without using an overwrite approach.Type: GrantFiled: February 23, 1994Date of Patent: October 10, 1995Assignee: International Business Machines CorporationInventors: Hideto Niijima, Hideo Asano, Yoshinori Sakaue, Takashi Toyooka -
Patent number: 5448733Abstract: This is a variable length data search apparatus which uses a latch, added to each word of a cell array. In this apparatus, the search operation is self controlled by using the previous matching signals stored in the latches. A character string (ABCA), from a data string (BABCABB . . . ), is stored, in order, in an associative memory containing, e.g., six rows having addresses 1 to 6, and the first character of the data string is sent to a buffer and a comparison is made. This sequence is repeated for each character but now the comparison is made only at the cell rows addresses which are adjacent the cell rows, which matched the previous character. This means that even if the length of the search character string is a variable length, only the number of times the comparison operation is repeated varies and this permits the search to be completed in an extremely short time as compared to the prior art.Type: GrantFiled: July 14, 1994Date of Patent: September 5, 1995Assignee: International Business Machines Corp.Inventors: Akashi Satoh, Hideto Niijima