Patents by Inventor Hideto Noguchi
Hideto Noguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11494638Abstract: A learning support device stores, as execution information, a set of an input value, an execution output value as an execution result and an expected output value, for a machine learning program. An arithmetic device generates an output value different from the expected output value as a teacher output value in accordance with a predetermined rule when the execution output value and the expected output value for a predetermined input value match each other, generates a loss function based on a difference between the teacher output value and the execution output value, generates a change value indicating a change in the loss function for each parameter in the neural network, calculates an influence degree of predetermined learning by calculating influence of an update value of the parameter obtained by the learning on the change value, and determines whether or not the update value is adopted based on the influence degree.Type: GrantFiled: May 15, 2019Date of Patent: November 8, 2022Assignee: HITACHI, LTD.Inventors: Naoto Sato, Hironobu Kuruma, Yuichiroh Nakagawa, Hideto Noguchi
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Patent number: 11481692Abstract: A validity of a prediction model can be evaluated comprehensively. A machine learning program verification apparatus 100 includes a calculation device 104. The calculation device 104 obtains a decision tree logical expression by logically combining path logical expressions indicating decision tree paths indecision trees for a program created by machine learning, creates a combined logical expression by logically combining a verification property logical expression and an objective variable calculation logical expression with the decision tree logical expression, performs satisfiability determination by inputting the combined logical expression to a satisfiability determiner, and when a result of the determination indicates satisfaction, obtains, from a satisfaction solution of the satisfiability determination, a violation input value that is a value of an explanatory variable that violates a verification property and a violation output value that is a value of an objective variable.Type: GrantFiled: February 7, 2020Date of Patent: October 25, 2022Assignee: HITACHI, LTD.Inventors: Naoto Sato, Yuichiroh Nakagawa, Hironobu Kuruma, Hideto Noguchi
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Publication number: 20210357695Abstract: A learning dataset generation support device 100 is configured to include: a storage device 101 that is configured to store a plurality of pieces of learning data used for supervised machine learning along with correct answer labels; and a computing device 104 that is configured to perform a process of sequentially acquiring the pieces of learning data from the storage device to extract feature vectors, an editing process of adding and/or deleting a feature vector according to a predetermined algorithm, and a process of generating learning data from the edited feature vectors.Type: ApplicationFiled: March 15, 2021Publication date: November 18, 2021Inventors: Hironobu KURUMA, Naoto SATO, Makoto ISHIKAWA, Kyohei OYAMA, Hideto NOGUCHI
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Patent number: 11080173Abstract: The boundary search test support device includes: a storage device that holds a plurality of input vectors; and an arithmetic device that executes a test by sequentially inputting the input vectors to a program generated by a neural network and acquiring output vectors which are test results, respectively generates, in a coordinate system which takes each of a predetermined plurality of elements among elements constituting the output vectors as a coordinate axis, a straight line in which the plurality of elements has a same value and a hyperplane in which a sum of values of the plurality of elements is taken as a predetermined value, and arranges a most antagonistic point and boundary vectors whose values of the elements rank higher than or equal to a predetermined ranking among the output vectors in the coordinate system, and outputs the coordinate system together with input vectors corresponding to the boundary vectors.Type: GrantFiled: January 11, 2019Date of Patent: August 3, 2021Assignee: HITACHI, LTD.Inventors: Naoto Sato, Tomoyuki Myojin, Hironobu Kuruma, Yuichiroh Nakagawa, Hideto Noguchi
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Patent number: 10789155Abstract: A coverage test support device includes a memory device that stores a test case and specification content of each of a plurality of coverage indexes, and an arithmetic device that sequentially gives a test input value of each pair in the test case to a program created by a neural network, executes a predetermined number of tests, and acquires a test result of the tests and neuron information at the time of test execution, applies the acquired neuron information to the specification content of each coverage indexes and calculates a value for each coverage index, and identifies, among the coverage indexes, a coverage index in which an elongation rate of the calculated value shows a predetermined tendency, as a preferential coverage index that is to be used preferentially, when either the number of executions of the tests or the number of bugs in the test result exceeds a predetermined standard.Type: GrantFiled: December 21, 2018Date of Patent: September 29, 2020Assignee: HITACHI, LTD.Inventors: Naoto Sato, Tomoyuki Myojin, Yuichiroh Nakagawa, Hironobu Kuruma, Hideto Noguchi
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Publication number: 20200265342Abstract: A validity of a prediction model can be evaluated comprehensively. A machine learning program verification apparatus 100 includes a calculation device 104. The calculation device 104 obtains a decision tree logical expression by logically combining path logical expressions indicating decision tree paths indecision trees for a program created by machine learning, creates a combined logical expression by logically combining a verification property logical expression and an objective variable calculation logical expression with the decision tree logical expression, performs satisfiability determination by inputting the combined logical expression to a satisfiability determiner, and when a result of the determination indicates satisfaction, obtains, from a satisfaction solution of the satisfiability determination, a violation input value that is a value of an explanatory variable that violates a verification property and a violation output value that is a value of an objective variable.Type: ApplicationFiled: February 7, 2020Publication date: August 20, 2020Inventors: Naoto SATO, Yuichiroh NAKAGAWA, Hironobu KURUMA, Hideto NOGUCHI
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Publication number: 20190362228Abstract: A learning support device stores, as execution information, a set of an input value, an execution output value as an execution result and an expected output value, for a machine learning program. An arithmetic device generates an output value different from the expected output value as a teacher output value in accordance with a predetermined rule when the execution output value and the expected output value for a predetermined input value match each other, generates a loss function based on a difference between the teacher output value and the execution output value, generates a change value indicating a change in the loss function for each parameter in the neural network, calculates an influence degree of predetermined learning by calculating influence of an update value of the parameter obtained by the learning on the change value, and determines whether or not the update value is adopted based on the influence degree.Type: ApplicationFiled: May 15, 2019Publication date: November 28, 2019Inventors: Naoto SATO, Hironobu KURUMA, Yuichiroh NAKAGAWA, Hideto NOGUCHI
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Publication number: 20190220388Abstract: The boundary search test support device includes: a storage device that holds a plurality of input vectors; and an arithmetic device that executes a test by sequentially inputting the input vectors to a program generated by a neural network and acquiring output vectors which are test results, respectively generates, in a coordinate system which takes each of a predetermined plurality of elements among elements constituting the output vectors as a coordinate axis, a straight line in which the plurality of elements has a same value and a hyperplane in which a sum of values of the plurality of elements is taken as a predetermined value, and arranges a most antagonistic point and boundary vectors whose values of the elements rank higher than or equal to a predetermined ranking among the output vectors in the coordinate system, and outputs the coordinate system together with input vectors corresponding to the boundary vectors.Type: ApplicationFiled: January 11, 2019Publication date: July 18, 2019Inventors: Naoto SATO, Tomoyuki MYOJIN, Hironobu KURUMA, Yuichiroh NAKAGAWA, Hideto NOGUCHI
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Publication number: 20190196943Abstract: A coverage test support device includes a memory device that stores a test case and specification content of each of a plurality of coverage indexes, and an arithmetic device that sequentially gives a test input value of each pair in the test case to a program created by a neural network, executes a predetermined number of tests, and acquires a test result of the tests and neuron information at the time of test execution, applies the acquired neuron information to the specification content of each coverage indexes and calculates a value for each coverage index, and identifies, among the coverage indexes, a coverage index in which an elongation rate of the calculated value shows a predetermined tendency, as a preferential coverage index that is to be used preferentially, when either the number of executions of the tests or the number of bugs in the test result exceeds a predetermined standard.Type: ApplicationFiled: December 21, 2018Publication date: June 27, 2019Applicant: HITACHI, LTD.Inventors: Naoto SATO, Tomoyuki MYOJIN, Yuichiroh NAKAGAWA, Hironobu KURUMA, Hideto NOGUCHI
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Patent number: 9779009Abstract: When verifying rapidly the equivalence between source codes with respect to refactoring, the present invention performs two types of verification: verification based on structural comparison using structure graphs obtained by analyzing the source codes, and verification based on symbolic execution. If the structural comparison using the structure graphs can verify that the structures are identical with each other, then symbolic execution is not performed. Further, before the verification based on the structural comparison, the structure graphs of the source codes before and after refactoring are normalized on the basis of normalization information, which is defined for each refactoring pattern, and thereby adjusted so that the resulting structures are identical with each other when the refactoring is valid.Type: GrantFiled: August 28, 2013Date of Patent: October 3, 2017Assignee: Hitachi, Ltd.Inventors: Yasufumi Suzuki, Daisuke Shimbara, Makoto Ichii, Hideto Noguchi
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Publication number: 20160179653Abstract: When verifying rapidly the equivalence between source codes with respect to refactoring, the present invention performs two types of verification: verification based on structural comparison using structure graphs obtained by analyzing the source codes, and verification based on symbolic execution. If the structural comparison using the structure graphs can verify that the structures are identical with each other, then symbolic execution is not performed. Further, before the verification based on the structural comparison, the structure graphs of the source codes before and after refactoring are normalized on the basis of normalization information, which is defined for each refactoring pattern, and thereby adjusted so that the resulting structures are identical with each other when the refactoring is valid.Type: ApplicationFiled: August 28, 2013Publication date: June 23, 2016Inventors: Yasufumi SUZUKI, Daisuke SHIMBARA, Makoto ICHII, Hideto NOGUCHI
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Publication number: 20150199183Abstract: An object is to assist analysis work on a program in software development and improve program development efficiency. A program analysis apparatus performs symbolic-execution on a program stored in a storage device, receives an input of a change point of the program, and based on a result of the symbolic-execution, identifies an influenced segment of the program when the program is changed for the change point. The program analysis apparatus receives the change point by receiving a change operation on any one of a symbolic summary which is a terminal node of an execution tree obtained by the symbolic-execution, a decision table based on the symbolic summary, and a source code. The program analysis apparatus visualizes the influenced segment of the identified program in any mode of the symbolic summary, the source code, and the decision table.Type: ApplicationFiled: January 13, 2015Publication date: July 16, 2015Applicant: HITACHI, LTD.Inventors: Yuichiro NAKAGAWA, Yasufumi SUZUKI, Makoto ICHII, Hideto NOGUCHI
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Patent number: 9027002Abstract: A method of converting a source code for converting a source code of software to an inspection code by using a computer, including the steps of: inputting a source code of software; inputting a plurality of different conversion rules; inputting a nonfunctional rule that is a constraint relating to process performance; and converting the source code to a nonfunctional inspection code written in an input language of a validation tool by the plurality of different conversion rules and the nonfunctional rule.Type: GrantFiled: October 25, 2011Date of Patent: May 5, 2015Assignee: Hitachi, Ltd.Inventors: Masaki Chikahisa, Makoto Ichii, Hideto Noguchi
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Publication number: 20130263092Abstract: A method of converting a source code for converting a source code of software to an inspection code by using a computer, including the steps of: inputting a source code of software; inputting a plurality of different conversion rules; inputting a nonfunctional rule that is a constraint relating to process performance; and converting the source code to a nonfunctional inspection code written in an input language of a validation tool by the plurality of different conversion rules and the nonfunctional rule.Type: ApplicationFiled: October 25, 2011Publication date: October 3, 2013Applicant: Hitachi,Ltd.Inventors: Masaki Chikahisa, Makoto Ichii, Hideto Noguchi
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Publication number: 20130239098Abstract: In checking a model of software, there is an approach of transforming a source code of software into a checking code in order to reduce a cost required to describe the checking code by an input language of a model checker. Since a user may select only a single transformation method, there are problems in that an abstraction-level change is difficult, a rule modification cost for following up a design and a change of the source code is high, and a rule modification cost for checking using another checking tool is high. In the present invention, when the source code is transformed into the checking code, a unit that selects a plurality of transformation rules is provided to allow the user to easily change an abstraction level. Further, the plurality of transformation rules include a transformation rule of transforming the source code into an intermediate format, a transformation rule of abstracting the intermediate format, and a transformation rule of transforming the intermediate format into the checking code.Type: ApplicationFiled: August 8, 2011Publication date: September 12, 2013Inventors: Makoto Ichii, Masaki Chikahisa, Hideto Noguchi, Takehiko Nagano
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Patent number: 7530276Abstract: This invention aims to realize reduction in size without impairing measurement accuracy or connection reliability in a semiconductor pressure sensor in which a glass substrate is adhered to a rear-surface side of a pressure-sensitive chip in which piezoresistive pressure-sensitive gauges have been formed on a front surface of a diaphragm formed of a silicon single crystal to form a space between a rear surface of the diaphragm and the glass substrate, for measuring a pressure applied to the front surface of the diaphragm with reference to a pressure of the first space as a standard pressure. In order to achieve this object, the semiconductor pressure sensor includes resinous projections formed on pressure-sensitive gauge electrodes disposed on a front surface of the pressure-sensitive chip or on wiring from the pressure-sensitive gauge electrodes and bumps formed so as to partially or entirely cover the resinous projections.Type: GrantFiled: August 22, 2007Date of Patent: May 12, 2009Assignee: Fujikura Ltd.Inventors: Masakazu Sato, Tatsuya Ito, Hideto Noguchi
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Publication number: 20080216075Abstract: An apparatus for supporting creation of a program includes: a program execution module (25) which reads a program (60) including a random output block (64) from a storage device (30), executes a program with a test input value, and obtains an execution result of the program; a model execution module (22) which reads a model (40) including a random output model block (44) from the storage device (30), executes the model on the test input value using a model execution tool, and obtains an execution result of the model; and a cross-checking module (28) which compares the execution result obtained by the program execution module (25) and the execution result obtained by the model execution module (22). The model execution module (22) obtains an output value of the random output block which is outputted as a result of execution of the program, and uses the output value of the random output block (64) as an output value of the random output model block (44) in the model.Type: ApplicationFiled: January 4, 2008Publication date: September 4, 2008Inventors: Kenji Ogasawara, Akihiko Koga, Hideto Noguchi
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Publication number: 20080173096Abstract: This invention aims to realize reduction in size without impairing measurement accuracy or connection reliability in a semiconductor pressure sensor in which a glass substrate is adhered to a rear-surface side of a pressure-sensitive chip in which piezoresistive pressure-sensitive gauges have been formed on a front surface of a diaphragm formed of a silicon single crystal to form a space between a rear surface of the diaphragm and the glass substrate, for measuring a pressure applied to the front surface of the diaphragm with reference to a pressure of the first space as a standard pressure. In order to achieve this object, the semiconductor pressure sensor includes resinous projections formed on pressure-sensitive gauge electrodes disposed on a front surface of the pressure-sensitive chip or on wiring from the pressure-sensitive gauge electrodes and bumps formed so as to partially or entirely cover the resinous projections.Type: ApplicationFiled: August 22, 2007Publication date: July 24, 2008Applicant: FUJIKURA LTD.Inventors: Masakazu SATO, Tatsuya Ito, Hideto Noguchi
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Patent number: 7284443Abstract: This invention aims to realize reduction in size without impairing measurement accuracy or connection reliability in a semiconductor pressure sensor in which a glass substrate is adhered to a rear-surface side of a pressure-sensitive chip in which piezoresistive pressure-sensitive gauges have been formed on a front surface of a diaphragm formed of a silicon single crystal to form a space between a rear surface of the diaphragm and the glass substrate, for measuring a pressure applied to the front surface of the diaphragm with reference to a pressure of the first space as a standard pressure. In order to achieve this object, the semiconductor pressure sensor includes resinous projections formed on pressure-sensitive gauge electrodes disposed on a front surface of the pressure-sensitive chip or on wiring from the pressure-sensitive gauge electrodes and bumps formed so as to partially or entirely cover the resinous projections.Type: GrantFiled: January 29, 2004Date of Patent: October 23, 2007Assignee: Fujikura Ltd.Inventors: Masakazu Sato, Tatsuya Ito, Hideto Noguchi
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Publication number: 20060185437Abstract: This invention aims to realize reduction in size without impairing measurement accuracy or connection reliability in a semiconductor pressure sensor in which a glass substrate is adhered to a rear-surface side of a pressure-sensitive chip in which piezoresistive pressure-sensitive gauges have been formed on a front surface of a diaphragm formed of a silicon single crystal to form a space between a rear surface of the diaphragm and the glass substrate, for measuring a pressure applied to the front surface of the diaphragm with reference to a pressure of the first space as a standard pressure. In order to achieve this object, the semiconductor pressure sensor includes resinous projections formed on pressure-sensitive gauge electrodes disposed on a front surface of the pressure-sensitive chip or on wiring from the pressure-sensitive gauge electrodes and bumps formed so as to partially or entirely cover the resinous projections.Type: ApplicationFiled: January 29, 2004Publication date: August 24, 2006Inventors: Masakazu Sato, Tatsuya Ito, Hideto Noguchi