Patents by Inventor Hideto Sugawara

Hideto Sugawara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11908972
    Abstract: A semiconductor light-emitting device includes a substrate having a first energy bandgap, a first semiconductor layers on the substrate, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer. The active layer includes a quantum well layer, and a first barrier layer between the first semiconductor layer and the quantum well layer. The first semiconductor layer has a second energy bandgap wider than the first energy bandgap. The quantum well layer has a third energy bandgap narrower than the first and second energy bandgaps. The second semiconductor layer has a fourth energy bandgap wider than the third energy bandgap. The substrate has a refractive index greater than a refractive index of the first semiconductor layer. The refractive index of the first semiconductor layer is not less than a refractive index of the first barrier layer.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: February 20, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Akira Tanaka, Hideto Sugawara, Katsufumi Kondo, Masanobu Iwamoto, Kenji Isomoto, Hiroaki Ootsuka
  • Patent number: 11728458
    Abstract: A semiconductor light-emitting device includes a semiconductor substrate and a light-emitting layer on the semiconductor substrate. The light-emitting layer includes at least one quantum well layer and barrier layers alternately stacked. The quantum well layer includes a first semiconductor mixed crystal having a larger lattice constant than a lattice constant of the semiconductor substrate. The barrier layers each includes a second semiconductor mixed crystal having a smaller lattice constant than the lattice constant of the semiconductor substrate. The quantum well layer includes a first strain amount that is a product of the layer thickness thereof and a first strain ratio. The barrier layer each includes a second strain amount that is a product of the layer thickness thereof and a second strain ratio. The quantum well layer and the barrier layers are provided such that the first strain amount is greater than the second strain amount.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: August 15, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hideto Sugawara
  • Publication number: 20230238483
    Abstract: A semiconductor light-emitting device includes a GaAs (gallium arsenide) substrate of a cubic crystal, a light-emitting layer and a multi-semiconductor layer. The light-emitting layer being provided on the GaAs substrate. The light-emitting layer includes InGaAs (indium gallium arsenide) represented by a compositional formula InxGa1-xAs (0<x<1). The multi-semiconductor layer being provided on a front surface of the GaAs substrate between the GaAs substrate and the light-emitting layer. The multi-semiconductor layer is tilted with respect to a (100) plane of the cubic crystal. The multi-semiconductor layer includes a first layer and a second layer. The first and second layers are alternately stacked in a direction perpendicular to the front surface of the GaAs substrate. The first layer is different in composition from the second layer.
    Type: Application
    Filed: August 26, 2022
    Publication date: July 27, 2023
    Inventors: Hideto SUGAWARA, Hiroaki OOTSUKA, Naoki MURAKAMI, Takanobu KAMAKURA
  • Patent number: 11694900
    Abstract: A semiconductor device includes an n-type semiconductor layer; a first metal layer provided on the n-type semiconductor layer, the first metal layer including first atoms capable of being n-type impurities in the n-type semiconductor layer; a second metal layer provided on the first metal layer, the second metal layer including titanium atoms; a third metal layer provided on the second metal layer; and a second atom capable of being a p-type impurity in the n-type semiconductor layer. The second atom and a part of the titanium atoms are included in a vicinity of an interface between the first metal layer and the second metal layer.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: July 4, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Toshiyuki Nishikawa, Kazuhiko Komatsu, Shinji Nunotani, Yoshiyuki Harada, Hideto Sugawara
  • Patent number: 11482645
    Abstract: A semiconductor light-emitting device includes first and second semiconductor layers and a light-emitting layer provided between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer includes a compound semiconductor represented by a compositional formula AlXGa1-XAs (0<X<1). The first semiconductor layer has an n-type conductivity and includes a first impurity of the n-type. The first layer further includes carbon with a lower concentration than a concentration of the first impurity, and oxygen with a lower concentration than the concentration of the first impurity. The second semiconductor layer includes a compound semiconductor represented by a compositional formula AlYGa1-YAs (0<Y<1). The second semiconductor layer has a p-type conductivity and including a second impurity of the p-type. The second semiconductor layer further includes carbon with a concentration substantially equal to the carbon concentration in the first semiconductor layer.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: October 25, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hideto Sugawara, Takanobu Kamakura
  • Publication number: 20220293817
    Abstract: A semiconductor light-emitting device includes a substrate having a first energy bandgap, a first semiconductor layers on the substrate, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer. The active layer includes a quantum well layer, and a first barrier layer between the first semiconductor layer and the quantum well layer. The first semiconductor layer has a second energy bandgap wider than the first energy bandgap. The quantum well layer has a third energy bandgap narrower than the first and second energy bandgaps. The second semiconductor layer has a fourth energy bandgap wider than the third energy bandgap. The substrate has a refractive index greater than a refractive index of the first semiconductor layer. The refractive index of the first semiconductor layer is not less than a refractive index of the first barrier layer.
    Type: Application
    Filed: September 3, 2021
    Publication date: September 15, 2022
    Inventors: Akira Tanaka, Hideto Sugawara, Katsufumi Kondo, Masanobu Iwamoto, Kenji Isomoto, Hiroaki Ootsuka
  • Publication number: 20220231191
    Abstract: A semiconductor light-emitting device includes a semiconductor substrate and a light-emitting layer on the semiconductor substrate. The light-emitting layer includes at least one quantum well layer and barrier layers alternately stacked. The quantum well layer includes a first semiconductor mixed crystal having a larger lattice constant than a lattice constant of the semiconductor substrate. The barrier layers each includes a second semiconductor mixed crystal having a smaller lattice constant than the lattice constant of the semiconductor substrate. The quantum well layer includes a first strain amount that is a product of the layer thickness thereof and a first strain ratio. The barrier layer each includes a second strain amount that is a product of the layer thickness thereof and a second strain ratio. The quantum well layer and the barrier layers are provided such that the first strain amount is greater than the second strain amount.
    Type: Application
    Filed: August 30, 2021
    Publication date: July 21, 2022
    Inventor: Hideto SUGAWARA
  • Publication number: 20220085241
    Abstract: A semiconductor light-emitting device includes first and second semiconductor layers and a light-emitting layer provided between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer includes a compound semiconductor represented by a compositional formula AlXGa1-XAs (0<X<1). The first semiconductor layer has an n-type conductivity and includes a first impurity of the n-type. The first layer further includes carbon with a lower concentration than a concentration of the first impurity, and oxygen with a lower concentration than the concentration of the first impurity. The second semiconductor layer includes a compound semiconductor represented by a compositional formula AlYGa1-YAs (0<Y<1). The second semiconductor layer has a p-type conductivity and including a second impurity of the p-type. The second semiconductor layer further includes carbon with a concentration substantially equal to the carbon concentration in the first semiconductor layer.
    Type: Application
    Filed: February 16, 2021
    Publication date: March 17, 2022
    Inventors: Hideto SUGAWARA, Takanobu KAMAKURA
  • Publication number: 20220020592
    Abstract: A semiconductor device includes an n-type semiconductor layer; a first metal layer provided on the n-type semiconductor layer, the first metal layer including first atoms capable of being n-type impurities in the n-type semiconductor layer; a second metal layer provided on the first metal layer, the second metal layer including titanium atoms; a third metal layer provided on the second metal layer; and a second atom capable of being a p-type impurity in the n-type semiconductor layer. The second atom and a part of the titanium atoms are included in a vicinity of an interface between the first metal layer and the second metal layer.
    Type: Application
    Filed: September 29, 2021
    Publication date: January 20, 2022
    Inventors: Toshiyuki NISHIKAWA, Kazuhiko KOMATSU, Shinji NUNOTANI, Yoshiyuki HARADA, Hideto SUGAWARA
  • Patent number: 11158514
    Abstract: A semiconductor device includes an n-type semiconductor layer; a first metal layer provided on the n-type semiconductor layer, the first metal layer including first atoms capable of being n-type impurities in the n-type semiconductor layer; a second metal layer provided on the first metal layer, the second metal layer including titanium atoms; a third metal layer provided on the second metal layer; and a second atom capable of being a p-type impurity in the n-type semiconductor layer. The second atom and a part of the titanium atoms are included in a vicinity of an interface between the first metal layer and the second metal layer.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: October 26, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Toshiyuki Nishikawa, Kazuhiko Komatsu, Shinji Nunotani, Yoshiyuki Harada, Hideto Sugawara
  • Publication number: 20210288159
    Abstract: Provided is a semiconductor device including: a group III-V semiconductor layer containing n-type impurities; a first conductive layer provided on the group III-V semiconductor layer, the first conductive layer containing titanium (Ti) and a first element that can be a p-type impurity of the group III-V semiconductor layer, the first conductive layer having a first region and a second region, a first element concentration of the second region being higher than that of the first region; and a second conductive layer provided on the first conductive layer.
    Type: Application
    Filed: September 4, 2020
    Publication date: September 16, 2021
    Inventors: Toshiyuki Nishikawa, Hideto Sugawara
  • Patent number: 11114822
    Abstract: According to one embodiment, an optical semiconductor element includes a substrate, a light emitting layer, and a distributed Bragg reflector. The light emitting layer includes an AlGaAs multi quantum well layer. The distributed Bragg reflector is provided between the substrate and the light emitting layer. A pair of a first layer and a second layer is periodically stacked in the distributed Bragg reflector. The first layer includes AlxGa1-xAs. The second layer includes Inz(AlyGa1-y)1-zP. A refractive index n1 of the first layer is higher than a refractive index n2 of the second layer. The first layer has a thickness larger than ?0/(4n1) where ?0 is a center wavelength of a band on wavelength distribution of a reflectivity of the distributed Bragg reflector. The second layer has a thickness smaller than ?0/(4n2).
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: September 7, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Masanobu Iwamoto, Hideto Sugawara, Kenji Isomoto
  • Patent number: 11114586
    Abstract: According to one embodiment, a semiconductor light emitting device includes a substrate, and a multi quantum well layer provided on the substrate, and including a plurality of barrier layers sandwiched between three or more InGaAs well layers and two InGaAs well layers. The barrier layers include at least two regions having different mixed crystal ratios or at least two regions having different thicknesses.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: September 7, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Hideto Sugawara
  • Publication number: 20210066888
    Abstract: According to one embodiment, an optical semiconductor element includes a substrate, a light emitting layer, and a distributed Bragg reflector. The light emitting layer includes an AlGaAs multi quantum well layer. The distributed Bragg reflector is provided between the substrate and the light emitting layer. A pair of a first layer and a second layer is periodically stacked in the distributed Bragg reflector. The first layer includes AlxGa1-xAs. The second layer includes Inz(AlyGa1-y)1-zP. A refractive index n1 of the first layer is higher than a refractive index n2 of the second layer. The first layer has a thickness larger than ?0/(4n1) where ?0 is a center wavelength of a band on wavelength distribution of a reflectivity of the distributed Bragg reflector. The second layer has a thickness smaller than ?0/(4n2).
    Type: Application
    Filed: February 13, 2020
    Publication date: March 4, 2021
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Masanobu IWAMOTO, Hideto Sugawara, Kenji Isomoto
  • Publication number: 20210057605
    Abstract: According to one embodiment, a semiconductor light emitting device includes a substrate, and a multi quantum well layer provided on the substrate, and including a plurality of barrier layers sandwiched between three or more InGaAs well layers and two InGaAs well layers. The barrier layers include at least two regions having different mixed crystal ratios or at least two regions having different thicknesses.
    Type: Application
    Filed: December 10, 2019
    Publication date: February 25, 2021
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Hideto SUGAWARA
  • Publication number: 20200303197
    Abstract: A semiconductor device includes an n-type semiconductor layer; a first metal layer provided on the n-type semiconductor layer, the first metal layer including first atoms capable of being n-type impurities in the n-type semiconductor layer; a second metal layer provided on the first metal layer, the second metal layer including titanium atoms; a third metal layer provided on the second metal layer; and a second atom capable of being a p-type impurity in the n-type semiconductor layer. The second atom and a part of the titanium atoms are included in a vicinity of an interface between the first metal layer and the second metal layer.
    Type: Application
    Filed: September 6, 2019
    Publication date: September 24, 2020
    Inventors: Toshiyuki Nishikawa, Kazuhiko Komatsu, Shinji Nunotani, Yoshiyuki Harada, Hideto Sugawara
  • Patent number: 10749022
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second, third, fourth, fifth, sixth and seventh semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on a portion of the first semiconductor region. The third semiconductor region is provided on another portion of the first semiconductor region. The fourth semiconductor region is provided in at least a portion between the first and third semiconductor regions. The fifth semiconductor region is provided between the first and fourth semiconductor regions. The sixth semiconductor region is provided on the third semiconductor region. The seventh semiconductor region is provided selectively on the sixth semiconductor region. The gate electrode opposes the second, sixth, and seventh semiconductor regions. The second electrode is provided on the sixth and seventh semiconductor regions.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: August 18, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Syotaro Ono, Hideto Sugawara, Hiroshi Ohta, Hisao Ichijo, Hiroaki Yamashita
  • Patent number: 10720523
    Abstract: A semiconductor device includes a semiconductor body, first and second electrodes, and a control electrode. The semiconductor body includes first to fourth semiconductor layers. The first electrode is provided on a front surface of the semiconductor body. The second electrode is provided on a back surface of the semiconductor body. The control electrode is provided between the semiconductor body and the first electrode. The second semiconductor layer is positioned between a portion and other portion of the first semiconductor layer in a first direction directed along the front surface. The third semiconductor layer contacts the portion of first semiconductor layer and the second semiconductor layer. The third semiconductor layer includes a first end portion positioned in the portion of the first semiconductor layer and a second end portion positioned in the second semiconductor layer. The fourth semiconductor layer is selectively provided in the second end portion.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: July 21, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hiroaki Yamashita, Syotaro Ono, Hisao Ichijo, Hideto Sugawara, Hiroshi Ohta
  • Publication number: 20200091335
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second, third, fourth, fifth, sixth and seventh semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on a portion of the first semiconductor region. The third semiconductor region is provided on another portion of the first semiconductor region. The fourth semiconductor region is provided in at least a portion between the first and third semiconductor regions. The fifth semiconductor region is provided between the first and fourth semiconductor regions. The sixth semiconductor region is provided on the third semiconductor region. The seventh semiconductor region is provided selectively on the sixth semiconductor region. The gate electrode opposes the second, sixth, and seventh semiconductor regions. The second electrode is provided on the sixth and seventh semiconductor regions.
    Type: Application
    Filed: March 4, 2019
    Publication date: March 19, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Syotaro ONO, Hideto Sugawara, Hiroshi Ohta, Hisao Ichijo, Hiroaki Yamashita
  • Publication number: 20200083320
    Abstract: A semiconductor device includes a semiconductor body including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The first and second semiconductor layers are alternately arranged in a first direction along a front surface of the semiconductor body, and each include multiple portions arranged in a second direction directed from a back surface toward the front surface of the semiconductor body. The first and second semiconductor layers are configured such that, in an active region, a large/small relationship between amounts of the first conductivity type impurity and the second conductivity type impurity in the portions positioned at the same level in the second direction reverses at a center in the second direction of the second semiconductor layer, and in the terminal region, the large/small relationship reverses alternately in the portions arranged in the second direction.
    Type: Application
    Filed: February 26, 2019
    Publication date: March 12, 2020
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hiroshi Ohta, Syotaro Ono, Hideto Sugawara, Hisao Ichijo, Hiroaki Yamashita