Abstract: A electric motor control device comprising a converter section converting AC voltage to DC voltage, an inverter section converting DC voltage from the converter section to AC voltage and supplying said AC voltage to electric motor, an inverter control unit controlling said inverter section, a current detection unit detecting the current flowing in said electric motors and a power calculation unit estimating the temperature of said electric motors from said detected current, calculating the resistance of said electric motors from said estimated temperature, and calculating the copper loss from said calculated resistance.

Abstract: A semiconductor integrated circuit includes a memory, a master interface circuit that performs one of receiving a data transfer request from the memory and outputting a data transfer request to the memory, a slave interface circuit that performs one of receiving data from the memory and outputting data to the memory in response to the data transfer requests, and a delay circuit that delays a data transfer end signal that indicates one of an end of a data transfer from the memory and an end of a data transfer to the memory.

Abstract: A semiconductor integrated circuit includes a memory, a master interface circuit that performs one of receiving a data transfer request from the memory and outputting a data transfer request to the memory, a slave interface circuit that performs one of receiving data from the memory and outputting data to the memory in response to the data transfer requests, and a delay circuit that delays a data transfer end signal that indicates one of an end of a data transfer from the memory and an end of a data transfer to the memory.

Abstract: In a video processor for compression encoding a series of picture elements of video data (frames or fields) based on macroblocks in some of the video data, each macroblock consisting of up to a predetermined number, such as 16×16, of picture elements in each video datum, a buffer stores the picture elements of the video datum. Controlled by a control signal produced in responses to the video data, an address signal is generated to assign the picture elements of each macroblock to one of memory sequences in one of parallel accessible banks of a frame memory, which is preferably a synchronous DRAM. The banks are allotted to each macroblock and two macroblocks which are contiguous to this each macroblock in each video datum in each macroblock row and each macroblock column, respectively. In this manner, the banks are allotted, when two in number, to the macroblocks which are arranged in each video datum in a checkered pattern.

Abstract: A digital audio signal processing circuit according to the present invention inputs a bit stream 1, which has a configuration including an additional information and several samples of the compressed audio signals, and decodes it. The input buffer size is designed by subtracting the size of inputting bits of the bit stream 1 while the signal processor 10 processes the sample from the total bits of the largest additional information and first sample.

Abstract: A speech signal processing circuit includes an input buffer for receiving inverse quantization samples and for temporarily storing those samples. The circuit also includes a band synthesis filter for reading the inverse quantization samples stored in the input buffer one by one, and for conducting quadrature conversion processing and sum-of-product operation processing to decode the samples into speech signals. The circuit further includes a control circuit for controlling operation of the band synthesis filter. When the inverse quantization samples are recognized as being stored in the input buffer, the control circuit controls the band synthesis filter to execute, as an initial operation, the quadrature conversion processing of the inverse quantization samples as many times as a number corresponding to an operation delay time of the band synthesis filter.

Abstract: The invention provides an ancillary data processing circuit wherein a bit train of ancillary data having a varying data length is converted into another bit train in units of a byte of a rearwardly packed form to make changing of byte boundaries in following processing unnecessary.

Abstract: An audio signal processing circuit has a synchronizing pattern detector, an unformatter, a synthesizing filter, an output latch, and a sequence generator. The sequence generator starts to operate the unformatter and the synthesizing filter from the time of the synchronizing pattern in the audio bit stream, and then temporarily stops the operation of the unformatter and the synthesizing filter when a first sample of the audio signal is stored in the output latch. In response to an audio start signal, the sequence generator starts to operate the unformatter and the synthesizing filter again to output an audio signal without a synchronization time error.

Abstract: In a synchronizing circuit receiving a bit stream including a synchronous pattern and various kinds of information bits, for outputting a synchronous signal, there is provided a synchronous pattern register which is previously set with known information bits of the layer, the bit rate and the sampling frequency. A synchronous pattern detecting circuit is configured not to recognize as a synchronous pattern, a synchronous pattern having the values other than previously set values. With this arrangement, it is possible to remarkably reduce probability that a quasi synchronous pattern is detected as the synchronous pattern, and therefore, it is possible to minimize missing of sound corresponding to the digital audio signal.

Abstract: The invention provides a synchronous circuit which prevents occurrence of a step-out condition even when an error in padding occurs. The synchronous circuit is applied to a digital transmission system wherein the number of bits in a frame varies periodically and bit number information is included in a frame. Making use of the fact that the bit number information has a periodicity, bit number information for one period is generated by a padding bit generator based on information from a synchronism detector to prevent occurrence of a step-out condition caused by an error in received bit number information.

Abstract: The invention provides a frequency subband encoding apparatus wherein the amount of comparison operation processing of a bit allocator is minimized. A subband filter divides a PCM signal into and outputs a plurality of frequency subbands. A SMR calculator calculates, for each of the frequency subbands, an SMR which is a ratio between a signal level and a mask level. A bit allocator calculates a reference NMR which is a value obtained by subtracting, from an SMR of the entire frequency band, a S/N ratio calculated from a reference bit number to be allocated to one of the frequency subbands which exhibits a maximum SMR, and adjusts the reference NMR to perform bit allocation to the frequency subbands.

Abstract: A logarithm computing circuit for fixed point numbers is disclosed that has: a shift number detection circuit that inputs a number of a fixed point representation, detects a shift number of the inputted number for the purpose of dividing the inputted number into an exponent part and a mantissa part, calculates an exponent part from the shift number and a radix point position of the inputted number, subtracts 1 from the exponent part, and finally outputs the subtraction result as an integer part; a shift circuit that normalizes the inputted number by shifting the inputted number a number of bits equal to the shift number and generates a mantissa part that is equal to or above 0.5 and below 1; and a decimal-part computing circuit that converts the mantissa part to its logarithm to base 2, adds 1 to the conversion result and outputs the result as a decimal part.

Abstract: A hardware arrangement for a fast Fourier Transform includes, an arithmetic unit for executing said fast Fourier Transform, a data memory for storing data to be executed and storing results thereof, and an address generator for generating addresses to be applied to said data memory. The hardware arrangement further is provided with a bit rotation circuit coupled to receive each of said addresses. The circuit rotates a predetermined number of lower bits of each of said addresses such as to locate the least significant bit at the upper bit position of said predetermined number of lower bits and shift the remaining bits towards the least significant bit by one.