Patents by Inventor Hidetomo Nishimura

Hidetomo Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200003969
    Abstract: An optical branch module including a glass block, an input/output gradient index lens, an output gradient index lens, a beam splitter film, a mirror film, an input optical fiber, a first output optical fiber that extracts input light from the input optical fiber reflected by the beam splitter film as first output light, and a second output optical fiber that extracts light passed through the beam splitter film passed through the glass block, reflected by the mirror film, passed through the glass block again, and input from the other end of the output gradient index lens as second output light.
    Type: Application
    Filed: January 10, 2018
    Publication date: January 2, 2020
    Inventors: Yuto YAMASHITA, Takayuki KIKUCHI, Fumiyasu SATOU, Hidetomo NISHIMURA
  • Publication number: 20120164815
    Abstract: There is provided a method of forming an element isolation layer, the method including: forming a pad oxide layer and a nitride layer in succession on a front face of a semiconductor substrate; forming a trench so as to penetrate through the pad oxide layer and the nitride layer and into the semiconductor substrate; forming an in-fill oxide layer so as to fill the trench and cover the nitride layer; polishing the in-fill oxide layer using a first polishing agent so as to leave in-fill oxide layer remaining over the nitride layer; and polishing the in-fill oxide layer using a second polishing agent having a polishing selectivity ratio of the in-fill oxide layer to the nitride layer greater than that of the first polishing agent, so as to expose the nitride layer and flatten the exposed faces of the nitride layer and the in-fill oxide layer.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 28, 2012
    Applicant: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hidetomo Nishimura
  • Publication number: 20110207290
    Abstract: A semiconductor device fabrication method deposits a dielectric stress-canceling film on oxide films formed on the surfaces of a semiconductor substrate and its isolation trenches, and partly etches the dielectric stress-canceling film to leave a dielectric base film inside each trench and a dielectric top film outside each trench. The trenches are then filled with a dielectric layer that covers the dielectric top and base films, the upper part of this dielectric layer is removed to expose the dielectric top films, and the dielectric top films are selectively etched, using the trench-filling dielectric layer as an etching mask. In the resulting trench isolation structure, the trenches are completely filled with dielectric material, and stress exerted by the oxide films in the trenches during heat treatment is canceled by opposing stress exerted by the dielectric base films.
    Type: Application
    Filed: January 31, 2011
    Publication date: August 25, 2011
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Hidetomo Nishimura
  • Publication number: 20080296770
    Abstract: A semiconductor device of the present invention includes a semiconductor substrate; a diffusion layer formed about a surface of the semiconductor substrate; a first conductive layer formed on the semiconductor substrate, and an insulating layer formed on the semiconductor substrate after the first conductive layer and the diffusion layer are formed, and a second conductive layer formed on the insulating layer, and a first contact formed in the insulating layer, connecting the first conductive layer to the second conductive layer, and a second contact formed in the insulating layer, connecting the first conductive layer to the diffusion layer. In addition, a part of the diffusion layer extends to a lower portion of the first contact.
    Type: Application
    Filed: May 22, 2008
    Publication date: December 4, 2008
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventors: Hidetomo Nishimura, Katsutoshi Saeki
  • Publication number: 20060205134
    Abstract: A method for manufacturing a semiconductor device including sidewall insulating films with different thicknesses includes the steps of (a) selectively forming first and second gate electrode structures on first and second active regions of a silicon substrate respectively, (b) forming a first silicon oxide film on the first and second active regions, (c) forming first and second lightly-doped regions in the first and second active regions respectively, (d) removing the first silicon oxide film formed on the first active region while leaving the first silicon oxide film formed on the second active region, (e) forming an insulating film on the first region and an insulating film on the first silicon oxide film formed on the second active region, and (f) forming a first sidewall insulating film on a first gate electrode structure's sidewall while forming a second sidewall insulating film on a second gate electrode structure's sidewall.
    Type: Application
    Filed: February 28, 2006
    Publication date: September 14, 2006
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Hidetomo NISHIMURA
  • Patent number: 6475901
    Abstract: A semiconductor device including a semiconductor substrate, and a plurality of first interconnects formed over the semiconductor substrate. A first insulating layer covers the plurality of first interconnects, and a second insulating layer is formed between the plurality of first interconnects. The second insulating layer has substantially the same height as the plurality of first interconnects. An intermediate insulating layer is formed over the second insulating layer.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: November 5, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hidetomo Nishimura, Makiko Nakamura
  • Publication number: 20020072221
    Abstract: A semiconductor device includes a semiconductor substrate, and a plurality of first interconnects formed over the semiconductor substrate. A first insulating layer covers the plurality of first interconnects, and a second insulating layer is formed between the plurality of first interconnects. The second insulating layer has substantially the same height as the plurality of first interconnects. An intermediate insulating layer formed over the second insulating layer.
    Type: Application
    Filed: October 29, 2001
    Publication date: June 13, 2002
    Inventors: Hidetomo Nishimura, Makiko Nakamura
  • Patent number: 4085343
    Abstract: A rotor for a rotary electrical machine having a superconductive field winding, wherein thermal resistance means is arranged at contact parts between a damper, which is so disposed as to cover the superconductive field winding, and a damper support which supports the damper from the inner side thereof. A plurality of protuberances are formed on either said damper support or said damper for restricting heat flow between said damper and said damper support. It is possible to cause a cooling medium to flow through interstices which are defined at the contact parts between the damper and the damper support.
    Type: Grant
    Filed: June 2, 1976
    Date of Patent: April 18, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Kunio Hasegawa, Hidetomo Nishimura, Kiyoshi Yamaguchi