Patents by Inventor Hidetoshi Furukawa

Hidetoshi Furukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of making a semiconductor device including testing before thinning the semiconductor substrate
    Patent number: 6365513
    Abstract: A via hole having a bottom is formed in a substrate and then a conductor layer is formed at least over a sidewall of the via hole. Thereafter, the substrate is thinned by removing a portion of the substrate opposite to another portion of the substrate in which the via hole is formed such that the conductor layer is exposed.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: April 2, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hidetoshi Furukawa, Atsushi Noma, Tsuyoshi Tanaka, Hidetoshi Ishida, Daisuke Ueda
  • Method for producing semiconductor integrated circuit
    Patent number: 6329262
    Abstract: A semiconductor integrated circuit includes a thermal resistor which is made of a tungsten silicon nitride containing at least about 5% by weight of silicon and formed on a semiconductor substrate directly or via an insulating film. The semiconductor integrated circuit is produced by a method including the steps of: forming a tungsten silicide nitride film on a semiconductor substrate; patterning the tungsten silicide nitride film in a predetermined pattern to form a thermal resistor; and forming a pair of electrodes to be connected to the thermal resistor.
    Type: Grant
    Filed: February 24, 1999
    Date of Patent: December 11, 2001
    Inventors: Takeshi Fukuda, Hiroshi Takenaka, Hidetoshi Furukawa, Takeshi Fukui, Daisuke Ueda
  • Method of manufacturing a resistor in a semiconductor device
    Patent number: 6245628
    Abstract: A resistive area 7 is formed selectively on a semi-insulating substrate 1, and ohmic electrodes 10 are formed on both ends of the resistive area. Then a photo resist 14 having an opening 13 between the electrodes 10 is so formed as not completely across the resistive area 7. A desirable resistance value is thus obtained by removing the resistance area 7 by etching through the opening 13 gradually.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: June 12, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Takeshi Fukui, Hidetoshi Furukawa, Daisuke Ueda
  • Regulating resistor network, semiconductor device including the resistor network, and method for fabricating the device
    Publication number: 20010001493
    Abstract: A regulating resistor network includes a plurality of resistors connected in parallel to each other. Each of these resistors is cuttable by being irradiated with light, and a resistance value of the regulating resistor network is adjustable by cutting at least one of the resistors off.
    Type: Application
    Filed: January 5, 2001
    Publication date: May 24, 2001
    Inventors: Yukio Iwasaki, Hidetoshi Furukawa, Tsuyoshi Tanaka, Daisuke Ueda
  • Regulating resistor network, semiconductor device including the resistor network, and method for fabricating the device
    Patent number: 6201288
    Abstract: A regulating resistor network includes a plurality of resistors connected in parallel to each other. Each of these resistors is cuttable by being irradiated with light, and a resistance value of the regulating resistor network is adjustable by cutting at least one of the resistors off.
    Type: Grant
    Filed: November 2, 1999
    Date of Patent: March 13, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukio Iwasaki, Hidetoshi Furukawa, Tsuyoshi Tanaka, Daisuke Ueda
  • Semiconductor integrated circuit with tungston silicide nitride thermal resistor
    Patent number: 6025632
    Abstract: A semiconductor integrated circuit includes a thermal resistor which is made of a tungsten silicon nitride containing at least about 5% by weight of silicon and formed on a semiconductor substrate directly or via an insulating film. The semiconductor integrated circuit is produced by a method including the steps of: forming a tungsten silicide nitride film on a semiconductor substrate; patterning the tungsten silicide nitride film in a predetermined pattern to form a thermal resistor; and forming a pair of electrodes to be connected to the thermal resistor.
    Type: Grant
    Filed: December 11, 1997
    Date of Patent: February 15, 2000
    Assignee: Matsushita Electronics Corp.
    Inventors: Takeshi Fukuda, Hiroshi Takenaka, Hidetoshi Furukawa, Takeshi Fukui, Daisuke Ueda
  • Power amplification circuit
    Patent number: 5708292
    Abstract: Variations in the waveform of high-frequency signals amplified by a field-effect transistor (FET) in a power amplification circuit due to changes in temperature are reduced. A FET having an n-type active layer, a source electrode, a drain electrode and a gate electrode is formed on a (1 0 0)-crystal plane of a semi-insulating GaAs substrate. The FET is protected by a passivation film. The angle .theta., formed between the longitudinal axial direction of the gate electrode and the <0 -1 -1>-direction, is set at an angle of from 0.degree. to 90.degree. corresponding to the impurity concentration of the n-type active layer, in order that the temperature coefficient of the FET threshold voltage becomes substantially equal to the temperature coefficient of the gate bias voltage applied from a power supply to the gate electrode. If the angle .theta. is set at 45.degree., then the temperature coefficient of the FET threshold voltage becomes zero.
    Type: Grant
    Filed: August 28, 1996
    Date of Patent: January 13, 1998
    Assignee: Matsushita Electronics Corporation
    Inventors: Hidetoshi Furukawa, Daisuke Ueda