Patents by Inventor Hidetoshi Iwashita

Hidetoshi Iwashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9841919
    Abstract: An information processing apparatus, among a plurality of information processing apparatuses, to which one of pieces of local data is assigned, the pieces of local data having been obtained by dividing global data shared by the plurality of information processing apparatuses, includes: a storage unit that includes a first storage area sectioned into prescribed units, and stores local data; a processor that executes a process including: detecting a plurality of continuous sections to which the target local data is to be written in a second storage area that is sectioned into the prescribed units in the different information processing apparatus, on the basis of storage area information that identifies data to which the target local data corresponds in the global data; and extracting as many pieces of local data as specified by the number of the continuous sections and transmitting the data to the different information processing apparatus.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: December 12, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Hidetoshi Iwashita
  • Publication number: 20160132272
    Abstract: An information processing apparatus, among a plurality of information processing apparatuses, to which one of pieces of local data is assigned, the pieces of local data having been obtained by dividing global data shared by the plurality of information processing apparatuses, includes: a storage unit that includes a first storage area sectioned into prescribed units, and stores local data; a processor that executes a process including: detecting a plurality of continuous sections to which the target local data is to be written in a second storage area that is sectioned into the prescribed units in the different information processing apparatus, on the basis of storage area information that identifies data to which the target local data corresponds in the global data; and extracting as many pieces of local data as specified by the number of the continuous sections and transmitting the data to the different information processing apparatus.
    Type: Application
    Filed: October 20, 2015
    Publication date: May 12, 2016
    Applicant: FUJITSU LIMITED
    Inventor: Hidetoshi Iwashita
  • Patent number: 8892937
    Abstract: The control device detects a failed node in which a failure has occurred from a plurality of computation nodes included in a plurality of computation units included in the parallel computer. The control device chooses execution nodes for executing the program from the computation nodes of the parallel computer except the detected failed nodes based on the number of computation nodes needed to execute the program. The control device selects a paths to connect the computation nodes from a plurality of links each connecting two computation units adjacent to each other through a plurality of paths configured to connect computation nodes included in two computation units adjacent to each other in a one-to-one manner included in the links connecting two computation units adjacent to each other in the plurality of computation units including the choosed execution nodes except the path connected to the detected failed node.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: November 18, 2014
    Assignee: Fujitsu Limited
    Inventor: Hidetoshi Iwashita
  • Publication number: 20120246512
    Abstract: The control device detects a failed node in which a failure has occurred from a plurality of computation nodes included in a plurality of computation units included in the parallel computer. The control device chooses execution nodes for executing the program from the computation nodes of the parallel computer except the detected failed nodes based on the number of computation nodes needed to execute the program. The control device selects a paths to connect the computation nodes from a plurality of links each connecting two computation units adjacent to each other through a plurality of paths configured to connect computation nodes included in two computation units adjacent to each other in a one-to-one manner included in the links connecting two computation units adjacent to each other in the plurality of computation units including the choosed execution nodes except the path connected to the detected failed node.
    Type: Application
    Filed: January 18, 2012
    Publication date: September 27, 2012
    Applicant: FUJITSU LIMITED
    Inventor: Hidetoshi IWASHITA
  • Patent number: 7555745
    Abstract: A translator apparatus for analyzing a parallel language program and converting the parallel language program into a sequential language program that is subject to a distributed processing by a plurality of processors includes a parameter generating unit that generates a setting code for setting a value in a distribution parameter; and an index localizing unit that generates a localizing code for localizing a loop index and an array index based on the distribution parameter of which the value is set by the setting code generated.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: June 30, 2009
    Assignee: Fujitsu Limited
    Inventor: Hidetoshi Iwashita
  • Patent number: 7073167
    Abstract: A compiler has a detection unit, a conversion unit, and a expansion unit. The detection unit detects a predetermined target from an input source program. The conversion unit converts the target detected by the detection unit into a procedure call. The expansion unit generates an online code describing a definition of a procedure to be called by the procedure call obtained by the detection unit. The compiler outputs a program in which the target detected by the detection unit is replaced with a procedure call, and an online code corresponding to the procedure call.
    Type: Grant
    Filed: April 17, 2001
    Date of Patent: July 4, 2006
    Assignee: Fujitsu Limited
    Inventor: Hidetoshi Iwashita
  • Publication number: 20060010432
    Abstract: A translator apparatus for analyzing a parallel language program and converting the parallel language program into a sequential language program that is subject to a distributed processing by a plurality of processors includes a parameter generating unit that generates a setting code for setting a value in a distribution parameter; and an index localizing unit that generates a localizing code for localizing a loop index and an array index based on the distribution parameter of which the value is set by the setting code generated.
    Type: Application
    Filed: November 18, 2004
    Publication date: January 12, 2006
    Inventor: Hidetoshi Iwashita
  • Publication number: 20040205729
    Abstract: A compiler has a detection unit, a conversion unit, and a expansion unit. The detection unit detects a predetermined target from an input source program. The conversion unit converts the target detected by the detection unit into a procedure call. The expansion unit generates an online code describing a definition of a procedure to be called by the procedure call obtained by the detection unit. The compiler outputs a program in which the target detected by the detection unit is replaced with a procedure call, and an online code corresponding to the procedure call.
    Type: Application
    Filed: April 17, 2001
    Publication date: October 14, 2004
    Inventor: Hidetoshi Iwashita
  • Patent number: 5799183
    Abstract: A method for optimizing a program by performing a data batch transfer between a first and second memories when data is read from the second memory into the first memory and when the data is written from the first memory into the second memory. The optimization processing includes analyzing the preference order relation of the accesses, in a loop procedure having accesses to array data in the second memory, classifying the array accesses in the loop into groups that need to be shared in the storage regions in which the data are temporarily stored in the first memory, finding the sum of sets of access elements for the accesses pertaining to each of the groups, determining a range of transferring the data, and generating, outside the loop, an instruction code for batchwisely making accesses to the array data on a transfer range pertaining to each of the groups.
    Type: Grant
    Filed: May 13, 1994
    Date of Patent: August 25, 1998
    Assignee: Fujitsu Limited
    Inventor: Hidetoshi Iwashita