Patents by Inventor Hidetoshi Kawasaki

Hidetoshi Kawasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6652166
    Abstract: A photographic film cartridge includes a light-shielding cloth. The light-shielding cloth is subjected to napping with a coarse napping machine and then napping with a fine napping machine. The napping machines have napper rollers including a pile roller and a counter roller. The rotational speed of the pile roller of the fine napping machine is higher than that of the pile roller of the coarse napping machine, and the rotational speed of the counter roller of the coarse napping machine is higher than that of the counter roller of the fine napping machine. The napping is carried out so that the cloth thickness obtained by the fine napping machine is less than the cloth thickness obtained by the coarse napping machine. A further napping is carried out using the fine napping machine so that the cloth thickness is greater than that obtained by the coarse napping machine.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: November 25, 2003
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Hidetoshi Kawasaki, Kazunori Mizuno
  • Publication number: 20030133711
    Abstract: A photographic film cartridge includes a light-shielding cloth. The light-shielding cloth is subjected to napping with a coarse napping machine and then napping with a fine napping machine. The napping machines have napper rollers including a pile roller and a counter roller. The rotational speed of the pile roller of the fine napping machine is higher than that of the pile roller of the coarse napping machine, and the rotational speed of the counter roller of the coarse napping machine is higher than that of the counter roller of the fine napping machine. The napping is carried out so that the cloth thickness obtained by the fine napping machine is less than the cloth thickness obtained by the coarse napping machine. A further napping is carried out using the fine napping machine so that the cloth thickness is greater than that obtained by the coarse napping machine.
    Type: Application
    Filed: December 26, 2002
    Publication date: July 17, 2003
    Applicant: FUJI PHOTO FILM CO., LTD.
    Inventors: Hidetoshi Kawasaki, Kazunori Mizuno
  • Patent number: 6365925
    Abstract: A semiconductor device that is easily operated with a single positive voltage supply and exhibits an excellent linearity of mutual conductance and source-gate capacitance with regard to a gate voltage is provided. The semiconductor device comprises a second barrier layer of AlGaAs, a channel layer of InGaAs and a first barrier layer of AlGaAs that are stacked in this order on a substrate of GaAs with a buffer layer of u-GaAs between the substrate and the second barrier layer. Carrier supply regions doped with n-type impurity are formed in part of the first and second barrier layers. A low resistivity region including a high concentration of p-type impurity (Zn) is formed in the first barrier layer. The low resistivity region is buried in a high resistivity region and brought to contact with a gate electrode. Upon an application of positive voltage to the gate electrode, a carrier deficient region disappears in the channel layer and no parasitic resistance component remains.
    Type: Grant
    Filed: September 11, 1998
    Date of Patent: April 2, 2002
    Assignee: Sony Corporation
    Inventors: Ichiro Hase, Mitsuhiro Nakamura, Hidetoshi Kawasaki, Shinichi Wada
  • Publication number: 20010002706
    Abstract: A semiconductor device that is easily operated with a single positive voltage supply and exhibits an excellent linearity of mutual conductance and source-gate capacitance with regard to a gate voltage is provided. The semiconductor device comprises a second barrier layer of AlGaAs, a channel layer of InGaAs and a first barrier layer of AlGaAs that are stacked in this order on a substrate of GaAs with a buffer layer of u-GaAs between the substrate and the second barrier layer. Carrier supply regions doped with n-type impurity are formed in part of the first and second barrier layers. A low resistivity region including a high concentration of p-type impurity (Zn) is formed in the first barrier layer. The low resistivity region is buried in a high resistivity region and brought to contact with a gate electrode. Upon an application of positive voltage to the gate electrode, a carrier deficient region disappears in the channel layer and no parasitic resistance component remains.
    Type: Application
    Filed: September 11, 1998
    Publication date: June 7, 2001
    Inventors: ICHIRO HASE, MITSUHIRO NAKAMURA, HIDETOSHI KAWASAKI, SHINICHI WADA
  • Patent number: 6201269
    Abstract: For suppressing generation of leakage current and side-gate effect in a junction field effect transistor, a gate extension is formed on a semi-insulative compound semiconductor substrate in a manner to extend from a gate and to protrude outward beyond a channel transversely thereto, and an insulating layer is formed on the semi-insulative compound semiconductor substrate under the gate extension. A method of producing this transistor comprises the steps of first forming a channel and a source-drain on a substrate, then forming a gate on the channel together with a gate extension which extends from the gate and protrudes outward beyond the channel transversely thereto, and forming an insulating layer adjacently to the channel and the source-drain in such a manner that no gap is existent between the insulating layer and at least the channel.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: March 13, 2001
    Assignees: Sony Corporation, Sony Chemicals Corporation
    Inventors: Chiaki Takano, Hidetoshi Kawasaki, Masaru Wada
  • Patent number: 5900765
    Abstract: A transistor-bias voltage stabilizing circuit comprises a current saturating resistor connected in series to the output of an FET, the gate bias voltage of which is to be stabilized and a capacitor connected in parallel to the current saturating resistor. The transistor-bias voltage stabilizing circuit may comprise a voltage detecting circuit and a negative-feedback circuit connected between the input and output of an FET, the gate bias voltage of which is to be stabilized.
    Type: Grant
    Filed: March 5, 1997
    Date of Patent: May 4, 1999
    Assignee: Sony Corporation
    Inventors: Hidetoshi Kawasaki, Takahiro Ohgihara
  • Patent number: 5501407
    Abstract: A photo film cassette has a spool on which photo film is wound. A cassette shell contains the spool in rotatable fashion. A pair of light-trapping ribbons are respectively mounted inside a photo film passage port in the cassette shell, and prevents ambient light from entering the cassette shell through the passage port. The ribbons are constituted of warp pile fabric woven in a needle loom from warp threads, weft threads, and warp pile threads. A first one of the weft threads is passed under a first one of the warp threads, then passed over a first one of the warp pile threads, and subsequently passed under a second one of the warp threads. The pile fabric is woven so as to symmetrize the first and second warp threads relative to the first warp pile thread. It follows that the ribbons are woven to have the firmly retained warp pile threads that are difficult to drop away from the ribbons.
    Type: Grant
    Filed: April 12, 1994
    Date of Patent: March 26, 1996
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Hidetoshi Kawasaki
  • Patent number: 5341188
    Abstract: Light-trapping members are cut out of a ribbon consisting of a base fabric and piles. The piles of the ribbon are pressed against the peripheral surface of a thermal drum to be inclined in the width direction after the ribbon is passed through and twisted by a twister disposed close to the thermal drum. The light-trapping members with inclined piles are attached to a film passage mouth of a self-advancing-type photographic film cassette with the inclination of the piles directed to the outside of the film passage mouth, so that the leading end of a photographic film can be advanced smoothly by rotation of a spool through the light-trapping members to the outside of the cassette.
    Type: Grant
    Filed: April 21, 1993
    Date of Patent: August 23, 1994
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Hidetoshi Kawasaki, Kazunori Mizuno, Nobuo Sugiyama