Patents by Inventor Hidetoshi Kitaura

Hidetoshi Kitaura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088588
    Abstract: A power converter includes first and second components on which male and female fitting members of each of a plurality of pairs of fitting members are arranged, with a pair of first alignment keys formed in the first and second components as reference positions. The first and second components are coupled to each other by the female fitting member clamping an insertion portion of the male fitting member inserted between first and second clamping portions of the female fitting member arranged so as to face each other in a state where the pair of first alignment keys are positionally aligned. The first and second clamping portions are each bent so as to form one of protrusions toward one of surfaces thereof facing each other. A gap is formed in a distal end portion of each of the first and second clamping portions.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Motohiko FUJIMURA, Hiroshi OGURA, Kazuhiro NISHIKAWA, Yoshihiro KAWAKITA, Hidetoshi KITAURA
  • Publication number: 20240072476
    Abstract: An electric power converter includes a first board, a second board, and a first board-to-board connector that electrically and mechanically connects the first board and the second board. The first board-to-board connector includes a male fitting member and a female fitting member. Each of a first clamp portion and a second clamp portion of the female fitting member includes a first contact forming portion and a second contact forming portion that are curved in a protruding shape, and a first spring portion and a second spring portion that are connected to the first contact forming portion and the second contact portion, respectively, and that are curved in corrugated shapes. An insert clamped between the first contact forming portion and the second contact forming portion forms an electrical contact, and the first spring portion and the second spring portion are independently deformable.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 29, 2024
    Inventors: HIDETOSHI KITAURA, HIROSHI OGURA, MOTOHIKO FUJIMURA, KAZUHIRO NISHIKAWA, YOSHIHIRO KAWAKITA
  • Publication number: 20230037202
    Abstract: A power conversion device includes: circuit boards; at least one engagement member configured to engage a male engagement member with a female engagement member to allow the circuit boards to be electrically connected, the male engagement member being connected to one of the circuit boards and having a substantially flat plate-shaped insertion portion, the female engagement member being connected to another of the circuit boards and having first and second clamping portions disposed to face each other, and the engagement of the engagement members being made by clamping the insertion portion by the clamping portions; a differential amplifier configured to measure a voltage across the engagement member; an arithmetic unit configured to estimate a resistance value of the engagement member based on the measured voltage; and a power conversion circuit controller configured to perform notification on condition that the estimated resistance value exceeds a resistance threshold.
    Type: Application
    Filed: July 19, 2022
    Publication date: February 2, 2023
    Inventors: Motohiko FUJIMURA, Hiroshi OGURA, Yoshihiro KAWAKITA, Hidetoshi KITAURA
  • Patent number: 11515280
    Abstract: A mounting structure is used, which includes: a semiconductor element including an element electrode; a metal member; and a sintered body configured to bond the semiconductor element and the metal member is used, in which the sintered body contains a first metal and a second metal solid-dissolved in the first metal, the second metal is a metal having a diffusion coefficient in the first metal larger than a self-diffusion coefficient of the first metal, and a content ratio of the second metal relative to a total mass of the first metal and the second metal in the sintered body is equal to or lower than a solid solution limit of the second metal to the first metal.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: November 29, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kiyohiro Hine, Hidetoshi Kitaura, Akio Furusawa
  • Patent number: 11476399
    Abstract: A jointing material includes: at least one type of element at 0.1 wt % to 30 wt %, the element being capable of forming a compound with each of tin and carbon; and tin at 70 wt % to 99.9 wt % as a main component.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 18, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidetoshi Kitaura, Akio Furusawa, Kiyohiro Hine
  • Publication number: 20220045027
    Abstract: A semiconductor device includes an insulation board, an electrode provided on the insulation board, a bonding layer provided on the electrode and made of a sintered body of metal particles having an average particle size of nano-order, and a semiconductor element bonded to the electrode via the bonding layer. A layer thickness of the bonding layer is greater than or equal to 220 ?m and less than or equal to 700 ?m.
    Type: Application
    Filed: July 1, 2021
    Publication date: February 10, 2022
    Inventors: SHOZO OCHI, HIDETOSHI KITAURA
  • Patent number: 11135683
    Abstract: A solder alloy, includes: about 3 wt % to about 15 wt % of Sb; about 0.01 wt % to about 1.5 wt % of Te; and about 0.005 wt % to about 1 wt % of at least one element selected from the group consisting of Zn, Co, and Cr; and a balance of Sn.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: October 5, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidetoshi Kitaura, Akio Furusawa, Kiyohiro Hine
  • Patent number: 11040883
    Abstract: Provided is a graphite plate, consisting essentially of: graphite; and pores, wherein said graphite plate has a porosity from 1% to 30%. Further provided is a method for producing a graphite plate, including: applying welding pressure to at least one glass-like carbon material in a state in which said at least one glass-like carbon material is maintained in an inert atmosphere under heating conditions, to produce a graphite plate having a porosity from 1% to 30%.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: June 22, 2021
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hidetoshi Kitaura, Naomi Nishiki, Atsushi Tanaka, Kimiaki Nakaya
  • Patent number: 10960496
    Abstract: There is provided a solder alloy in which 0.5 mass % or more and 1.25 mass % or less of Sb, In satisfying the following formula (I) or (II) when [Sb] is set as a Sb content percentage (mass %) and [In] is set as an In content percentage (mass %): in a case of 0.5?[Sb]?1.0, 5.5?[In]?5.50+1.06[Sb] . . . (I), in a case of 1.0<[Sb]?1.25, 5.5?[In]?6.35+0.212[Sb] . . . (II) (in the formula, [Sb] indicates a Sb content percentage (mass %) and [In] indicates an In content percentage (mass %)), 0.5 mass % or more and 1.2 mass % or less of Cu, 0.1 mass % or more and 3.0 mass % or less of Bi, 1.0 mass % or more and 4.0 mass % or less of Ag, and 0 mass % or more and 0.025 mass % or less of Co are contained, and has the remainder consisting essentially of Sn.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: March 30, 2021
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Shinnosuke Akiyama, Kiyohiro Hine, Hidetoshi Kitaura, Akio Furusawa
  • Publication number: 20200185347
    Abstract: A mounting structure is used, which includes: a semiconductor element including an element electrode; a metal member; and a sintered body configured to bond the semiconductor element and the metal member is used, in which the sintered body contains a first metal and a second metal solid-dissolved in the first metal, the second metal is a metal having a diffusion coefficient in the first metal larger than a self-diffusion coefficient of the first metal, and a content ratio of the second metal relative to a total mass of the first metal and the second metal in the sintered body is equal to or lower than a solid solution limit of the second metal to the first metal.
    Type: Application
    Filed: February 13, 2020
    Publication date: June 11, 2020
    Inventors: KIYOHIRO HINE, HIDETOSHI KITAURA, AKIO FURUSAWA
  • Patent number: 10636724
    Abstract: A mount structure having a joining capable of withstanding development of cracks generated by thermal stress due to repeated temperature changes in a mount structure having the joining of a large area is formed by joining a ceramic substrate electrode of a ceramic substrate and a metal substrate electrode of a metal substrate by a laminate, in which the laminate is formed by stacking a first interface layer, a first solder joining portion, a second interface layer, a first buffer material electrode, a buffer material, a second buffer material electrode, a third interface layer, a second solder joining portion and a fourth interface layer in this order from the ceramic substrate electrode toward the metal substrate electrode, a thickness of the laminate is 30 ?m or more and 100 ?m or less, a difference between a thickness of the first solder joining portion and a thickness of the second solder joining portion is within 25%, and differences in elastic moduli and in linear expansion coefficients between the firs
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: April 28, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTTD.
    Inventors: Kiyohiro Hine, Akio Furusawa, Hidetoshi Kitaura, Kazuki Sakai
  • Patent number: 10493567
    Abstract: A solder alloy of the disclosure includes Sb of which a content is in a range of 3 wt % to 30 wt %, Te of which a content is in a range of 0.01 wt % to 1.5 wt %, Au of which a content is in a range of 0.005 wt % to 1 wt %, at least one of Ag and Cu, wherein a content rate of at least one of Ag and Cu in the solder alloy is in a range of 0.1 wt % to 20 wt %; and a content rate of a sum of Ag and Cu in the solder alloy is in a range of 0.1 wt % to 20 wt %; and a balance of Sn.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: December 3, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kazuki Sakai, Akio Furusawa, Hidetoshi Kitaura, Kiyohiro Hine
  • Patent number: 10435607
    Abstract: A graphite material has a flexible part and can be utilized as a heat-conveying material in a narrow space. The graphite material, includes: at least one heat-conveying part; and a flexible part. A method for producing a graphite material, includes: (i) subjecting at least one film serving as a material to a heat treatment to obtain at least one carbonaceous film; (ii) providing a monolayer or multilayer structure including the at least one carbonaceous film; and (iii) applying heat and pressure to at least one part of the monolayer or multilayer structure in an inert atmosphere.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: October 8, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Atsushi Tanaka, Naomi Nishiki, Hidetoshi Kitaura, Kimiaki Nakaya
  • Patent number: 10357942
    Abstract: A graphite-silicon composite, including: graphite; silicon; and an intermediate layer that is located between the graphite and the silicon, wherein the intermediate layer includes oxygen, carbon and silicon. Furthermore, provided is a method for producing a graphite-silicon composite, including: layering graphite and silicon; and heating the layered graphite and silicon while applying pressure to them, wherein, during heating the layered graphite and silicon while applying pressure to them, an oxygen concentration in the atmosphere is adjusted to 0.2 vol %, the applied pressure is adjusted to 24.5 MPa or higher, and the heating temperature is adjusted to 1260° C. or higher.
    Type: Grant
    Filed: July 9, 2016
    Date of Patent: July 23, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kazuhiro Nishikawa, Naomi Nishiki, Hidetoshi Kitaura, Atsushi Tanaka, Kimiaki Nakaya, Henrik Rønnow
  • Publication number: 20190165234
    Abstract: A jointing material includes: at least one type of element at 0.1 wt % to 30 wt %, the element being capable of forming a compound with each of tin and carbon; and tin at 70 wt % to 99.9 wt % as a main component.
    Type: Application
    Filed: November 20, 2018
    Publication date: May 30, 2019
    Inventors: Hidetoshi KITAURA, Akio FURUSAWA, Kiyohiro HINE
  • Publication number: 20190099840
    Abstract: A solder alloy, includes: about 3 wt % to about 15 wt % of Sb; about 0.01 wt % to about 1.5 wt % of Te; and about 0.005 wt % to about 1 wt % of at least one element selected from the group consisting of Zn, Co, and Cr; and a balance of Sn.
    Type: Application
    Filed: September 20, 2018
    Publication date: April 4, 2019
    Inventors: HIDETOSHI KITAURA, AKIO FURUSAWA, KIYOHIRO HINE
  • Patent number: 10170442
    Abstract: A mount structure includes two members that are bonded to each other with a bonding material layer having a first interface layer and a second interface layer at the interfaces with the two members. The bonding material layer contains a first intermetallic compound and a stress relaxation material. The first intermetallic compound has a spherical, a columnar, or an oval spherical shape, and the same crystalline structure as the first interface layer and the second interface layer, and partly closes the space between the first interface layer and the second interface layer. The stress relaxation material contains tin as a main component, and fills around the first intermetallic compound.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: January 1, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kiyohiro Hine, Akio Furusawa, Hidetoshi Kitaura, Kazuki Sakai
  • Publication number: 20180331013
    Abstract: A mount structure having a joining capable of withstanding development of cracks generated by thermal stress due to repeated temperature changes in a mount structure having the joining of a large area is formed by joining a ceramic substrate electrode of a ceramic substrate and a metal substrate electrode of a metal substrate by a laminate, in which the laminate is formed by stacking a first interface layer, a first solder joining portion, a second interface layer, a first buffer material electrode, a buffer material, a second buffer material electrode, a third interface layer, a second solder joining portion and a fourth interface layer in this order from the ceramic substrate electrode toward the metal substrate electrode, a thickness of the laminate is 30 ?m or more and 100 ?m or less, a difference between a thickness of the first solder joining portion and a thickness of the second solder joining portion is within 25%, and differences in elastic moduli and in linear expansion coefficients between the firs
    Type: Application
    Filed: April 10, 2018
    Publication date: November 15, 2018
    Inventors: KIYOHIRO HINE, AKIO FURUSAWA, HIDETOSHI KITAURA, KAZUKI SAKAI
  • Publication number: 20180326542
    Abstract: A solder alloy of the disclosure includes Sb of which a content is in a range of 3 wt % to 30 wt %, Te of which a content is in a range of 0.01 wt % to 1.5 wt %, Au of which a content is in a range of 0.005 wt % to 1 wt %, at least one of Ag and Cu, wherein a content rate of at least one of Ag and Cu in the solder alloy is in a range of 0.1 wt % to 20 wt %; and a content rate of a sum of Ag and Cu in the solder alloy is in a range of 0.1 wt % to 20 wt %; and a balance of Sn.
    Type: Application
    Filed: April 10, 2018
    Publication date: November 15, 2018
    Inventors: KAZUKI SAKAI, AKIO FURUSAWA, HIDETOSHI KITAURA, KIYOHIRO HINE
  • Patent number: 10085495
    Abstract: The clothing having a frontal land and a rear land includes: a thermal storage unit provided on at least one portion of the frontal land of the clothing; and a planar thermoconductive sheet located in a planar between the frontal land and the rear land, the planar thermoconductive sheet having a thermal conduction path to the thermal storage unit, and the planar thermoconductive sheet being higher in thermoconductivity than the frontal land and the rear land. The planar thermoconductive sheet includes a resin component and graphite particles. Basal plane of each graphite particle is parallel to the direction of the plane of the planar thermoconductive sheet.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: October 2, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidetoshi Kitaura, Naomi Nishiki, Kazuhiro Nishikawa, Kimiaki Nakaya, Atsushi Tanaka