Patents by Inventor Hidetoshi Matsuoka
Hidetoshi Matsuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230038440Abstract: A non-transitory computer-readable storage medium storing a route search program that causes a computer to execute a process that includes acquiring a storage period of an item for each point of a plurality of points in a case where the item is moved from a departure point to a destination point, the plurality of points including the departure point, the destination point, and one or more relay points; and searching for a route along which the item is moved from the departure point to the destination point based on a traveling cost, storage information, and the acquired storage period, a traveling cost indicating a cost for moving the item between each two points of the plurality of points, the storage information indicating a storage coefficient being used for calculation of a storage cost of the item at each point of the plurality of points in accordance with the storage period.Type: ApplicationFiled: May 19, 2022Publication date: February 9, 2023Applicant: FUJITSU LIMITEDInventors: MASAHARU HIDA, SATOSHI SHIMOKAWA, Hidetoshi MATSUOKA
-
Patent number: 11556849Abstract: A method includes: partitioning learning data containing objective variables and explanatory variables into a plurality of subsets of data; executing regularization processing on first data in each of the partitioned subsets, and extracting a first element equal to zero; extracting, as a candidate, each model where an error ratio between first multiple regression and second multiple regression is equal to or more than a predetermined value, the first multiple regression being a result of multiple regression on second data which is test data in each of the partitioned subsets and is for use to calculate the error ratio of the learning data, the second multiple regression being a result of multiple regression on third data obtained by excluding the first element from the second data; and outputting a model where zero is substituted for an element that takes zero a predetermined or larger number of times in the candidate.Type: GrantFiled: November 21, 2019Date of Patent: January 17, 2023Assignee: FUJITSU LIMITEDInventors: Takuya Ohwa, Hidetoshi Matsuoka
-
Patent number: 11544660Abstract: A method includes: for each of a delivery source and each of plural delivery destinations to which goods are delivered, receiving distance information indicating a distance between points, delivery amount information indicating a total delivery amount of the goods to each of the plural delivery destinations, and maximum delivery amount information indicating a maximum delivery amount per delivery; calculating a first cost to deliver the goods for the total delivery amount from the delivery source to each of the plural delivery destinations while setting the maximum delivery amount indicated by the maximum delivery amount information; calculating a second cost to deliver the goods for the total delivery amount from the delivery source to each of the delivery destinations; executing selection processing for selecting a delivery destination by using the first cost and the second cost; and creating a delivery plan by using a result of the selection processing.Type: GrantFiled: February 3, 2021Date of Patent: January 3, 2023Assignee: FUJITSU LIMITEDInventors: Kenji Nomura, Hideshi Yamaguchi, Hidetoshi Matsuoka
-
Publication number: 20220405351Abstract: A non-transitory computer-readable storage medium storing an optimization program that causes a computer to execute a process includes selecting a plurality of bits based on a constraint condition of an optimization problem for each of a plurality of first elements that are search targets of a solution, from bit group information indicating whether each of a plurality of second elements included in each of the plurality of first elements are selected to be used for searching for the solution; when the selected plurality of bits are accepted, inverting the plurality of bits in the bit group information; when the selected plurality of bits are not accepted, inverting the plurality of bits to return to a state before the determining in the bit group information; and searching for the solution of the optimization problem based on a selection status of each of the plurality of bits in the bit group information.Type: ApplicationFiled: March 3, 2022Publication date: December 22, 2022Applicant: FUJITSU LIMITEDInventors: KENJI NOMURA, Hidetoshi MATSUOKA
-
Patent number: 11526805Abstract: A method includes: partitioning learning data containing objective variables and explanatory variables into a plurality of subsets of data; executing regularization processing on first data in each of the partitioned subsets, and extracting a first element equal to zero; extracting, as a candidate, each model where an error ratio between first multiple regression and second multiple regression is equal to or more than a predetermined value, the first multiple regression being a result of multiple regression on second data which is test data in each of the partitioned subsets and is for use to calculate the error ratio of the learning data, the second multiple regression being a result of multiple regression on third data obtained by excluding the first element from the second data; and outputting a model where zero is substituted for an element that takes zero a predetermined or larger number of times in the candidate.Type: GrantFiled: November 21, 2019Date of Patent: December 13, 2022Assignee: FUJITSU LIMITEDInventors: Takuya Ohwa, Hidetoshi Matsuoka
-
NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM, SOLVING METHOD, AND INFORMATION PROCESSING DEVICE
Publication number: 20220122034Abstract: A non-transitory computer-readable recording medium storing a program that causes a computer to execute a process, the process includes generating, based on an index value related to an evaluation function value, a first candidate target from combinatorial targets in a combinatorial optimization problem that minimizes the evaluation function value under a plurality of constraint conditions, analyzing, based on a first result obtained by solving and optimizing based on the first candidate target, a combination that is included in the first result and that is a constraint violation, selecting, from among the combinatorial targets, a target related to resolving of the constraint violation that has been analyzed, obtaining, based on a second candidate target that include the selected combinatorial target and the first result, a second result which is optimized, and determining a solving result of the combinatorial optimization problem based on an evaluation result of the second result.Type: ApplicationFiled: July 22, 2021Publication date: April 21, 2022Applicant: FUJITSU LIMITEDInventors: Hiroyasu KAWANO, Hidetoshi MATSUOKA -
Publication number: 20210334745Abstract: A method includes: for each of a delivery source and each of plural delivery destinations to which goods are delivered, receiving distance information indicating a distance between points, delivery amount information indicating a total delivery amount of the goods to each of the plural delivery destinations, and maximum delivery amount information indicating a maximum delivery amount per delivery; calculating a first cost to deliver the goods for the total delivery amount from the delivery source to each of the plural delivery destinations while setting the maximum delivery amount indicated by the maximum delivery amount information; calculating a second cost to deliver the goods for the total delivery amount from the delivery source to each of the delivery destinations; executing selection processing for selecting a delivery destination by using the first cost and the second cost; and creating a delivery plan by using a result of the selection processing.Type: ApplicationFiled: February 3, 2021Publication date: October 28, 2021Applicant: FUJITSU LIMITEDInventors: KENJI NOMURA, Hideshi Yamaguchi, Hidetoshi MATSUOKA
-
Publication number: 20210256179Abstract: An information processing system includes: a processor configured to: acquire a plurality of solutions each represented by values of a plurality of variables included in an energy function; calculate, for each of a plurality of of a variable among the plurality of variables and a candidate value of the variable, an index indicating a possibility of a certain candidate value corresponding to a certain variable being included in a solution that is better than a currently obtained solution or in an optimal solution, based on the plurality of solutions and values of the energy function respectively corresponding to the plurality of solutions; and select one set based on the index calculated for each of the plurality of sets; and an output circuit configured to output an instruction to execute another search for another solution with the variable included in the selected one set fixed to the corresponding candidate value.Type: ApplicationFiled: January 19, 2021Publication date: August 19, 2021Applicant: FUJITSU LIMITEDInventors: Matthieu Parizy, Hidetoshi MATSUOKA
-
Publication number: 20210239481Abstract: A combinatorial optimization problem for acquiring a plurality of routes to be used by a traveling entity to visit a plurality of spot nodes and having a depot node as a starting point and end point of each of the routes is solved by a computer. The computer acquires a maximum number of spot nodes to be allocated to one route, determines the number of state variables to be used for formulating the combinatorial optimization problem based on the maximum number, generates, for the determined number of state variables, information on an objective function; and outputs the generated information on the objective function to a searching apparatus searching a ground state indicated by a set of the state variables included in the objective function.Type: ApplicationFiled: December 15, 2020Publication date: August 5, 2021Applicant: FUJITSU LIMITEDInventors: Satoshi HANDA, Matthieu Parizy, Hidetoshi MATSUOKA
-
Publication number: 20200338843Abstract: An information processing device includes: a memory; and a processor configured to: execute an annealing operation; hold a temperature corresponding to replica state identification information that identifies a replica state corresponding to an annealing operation of N times previously executed, parameters, and energy; calculate a barycenter of parameters corresponding to each replica state of N times; determine whether a barycenter is within a predetermined distance, for each of sets of replica states corresponding to a temperature equal to or lower than a predetermined temperature; change a temperature corresponding to any one of replica states in a set of replica states determined to have a barycenter within the predetermined distance, to a temperature exceeding the predetermined temperature; and use the changed temperature and a parameters corresponding to a replica state corresponding to the temperature, to perform the annealing operation.Type: ApplicationFiled: March 25, 2020Publication date: October 29, 2020Applicant: FUJITSU LIMITEDInventors: Matthieu Parizy, Hidetoshi Matsuoka
-
Publication number: 20200184375Abstract: A method includes: partitioning learning data containing objective variables and explanatory variables into a plurality of subsets of data; executing regularization processing on first data in each of the partitioned subsets, and extracting a first element equal to zero; extracting, as a candidate, each model where an error ratio between first multiple regression and second multiple regression is equal to or more than a predetermined value, the first multiple regression being a result of multiple regression on second data which is test data in each of the partitioned subsets and is for use to calculate the error ratio of the learning data, the second multiple regression being a result of multiple regression on third data obtained by excluding the first element from the second data; and outputting a model where zero is substituted for an element that takes zero a predetermined or larger number of times in the candidate.Type: ApplicationFiled: November 21, 2019Publication date: June 11, 2020Applicant: FUJITSU LIMITEDInventors: Takuya OHWA, Hidetoshi MATSUOKA
-
Publication number: 20160378767Abstract: An information extraction method, includes: extracting, by a computer, a plurality of item candidates that are candidates of Pareto-optimal items from among items included in item information, based on a search condition; obtaining an order of the plurality of candidates based on history information indicating previously-selected items; calculating a score for each of one or more first items that do not satisfy the search condition and is included in the item information based on the order; and outputting one or more second items having a score which satisfies a specific condition from among the one or more first items based on the score.Type: ApplicationFiled: April 13, 2016Publication date: December 29, 2016Applicant: FUJITSU LIMITEDInventors: Tatsuya Yamamoto, Hidetoshi MATSUOKA
-
Patent number: 9384860Abstract: A semiconductor memory includes a memory cell array that includes data cells of x bits and redundant cells of y bits for each word; a position-data storage unit that stores, for each word, defective-cell position data of defective cells of the data cells and the redundant cells; and a read circuit that reads data from cells of x bits based on the defective-cell position data stored in the position-data storage unit for a specified word of which address is specified as read address, the cells of x bits being formed by the data cells of x bits and the redundant cells of y bits of the specified word other than the defective cells.Type: GrantFiled: July 15, 2014Date of Patent: July 5, 2016Assignee: FUJITSU LIMITEDInventors: Yoshinori Tomita, Hidetoshi Matsuoka, Hiroyuki Higuchi
-
Patent number: 9064070Abstract: Disclosed is a simulation method for simulating an operation of a device. The simulation method includes specifying, by a computer, a boundary between a non-defective status and a defective status of a product in design space with a design parameter as an origin. The boundary is specified according to a search using a search indicator defined based on an operating state different from an operating state of a determination indicator that determines the non-defective status and the defective status of the operation.Type: GrantFiled: February 7, 2011Date of Patent: June 23, 2015Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Hiroshi Ikeda, Hidetoshi Matsuoka
-
Publication number: 20140321222Abstract: A semiconductor memory includes a memory cell array that includes data cells of x bits and redundant cells of y bits for each word; a position-data storage unit that stores, for each word, defective-cell position data of defective cells of the data cells and the redundant cells; and a read circuit that reads data from cells of x bits based on the defective-cell position data stored in the position-data storage unit for a specified word of which address is specified as read address, the cells of x bits being formed by the data cells of x bits and the redundant cells of y bits of the specified word other than the defective cells.Type: ApplicationFiled: July 15, 2014Publication date: October 30, 2014Applicant: FUJITSU LIMITEDInventors: Yoshinori TOMITA, Hidetoshi MATSUOKA, Hiroyuki HIGUCHI
-
Patent number: 8732643Abstract: A design support apparatus includes a detecting unit, a determining unit, and an inserting unit. The detecting unit detects a via that connects wirings in a circuit to be designed that is expressed by layout information. The determining unit determines the connection position of a dummy via that does not connect wirings, to be on at least one of wirings connected to the via detected by the detecting unit. The inserting unit inserts the dummy via at the connection position determined by the determining unit.Type: GrantFiled: June 17, 2010Date of Patent: May 20, 2014Assignee: Fujitsu LimitedInventor: Hidetoshi Matsuoka
-
Patent number: 8713489Abstract: A parameter correction method includes: obtaining, from a variability-aware simulation, a simulation result value of a predetermined product performance for a reference candidate value set concerning statistics of predetermined product characteristics; calculating a likelihood by substituting the reference candidate value set, the obtained simulation result value, statistics of measurement values of the predetermined product characteristics and a measurement value of the predetermined product performance into a likelihood function that is defined from a probability density function for the statistics of the predetermined product characteristics and a probability density function for the predetermined product performance, and is a function to calculate a combined likelihood of the statistics of the predetermined product characteristics and the predetermined product performance; and searching for a reference candidate value set in case where the calculated likelihood becomes maximum, by carrying out the obtainiType: GrantFiled: March 21, 2011Date of Patent: April 29, 2014Assignee: Fujitsu LimitedInventors: Hiroyuki Higuchi, Hidetoshi Matsuoka
-
Patent number: 8694289Abstract: A non-transitory computer-readable recording medium stores therein a model generating program that causes a computer capable of accessing a memory device storing, among coefficients and input variables making up a model formula expressing an object to be modeled, statistical values associated with the coefficients to execute: inputting a data group as a combination of an input value and an output value with respect to the object; determining, based on a joint probability joining a first probability of occurrence of the model formula as defined by the statistical values and the coefficients and a second probability of occurrence of the model formula as defined by the input variables and output variables, values of the coefficients to maximize the joint probability by giving the data group to the input variables and the output variables of the joint probability; and outputting the values of the coefficients determined in relation to the model formula.Type: GrantFiled: October 12, 2010Date of Patent: April 8, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Hidetoshi Matsuoka
-
Patent number: 8418089Abstract: A computer readable non-transitory medium storing a design aiding program causes a computer to execute a process of determining worst-case corner candidates for each of a plurality of condition sets. The design aiding program causes the computer to execute a process of mapping the worst-case corner candidates that are within an allowable range. The design aiding program causes a computer to execute a process of determining the worst-case corner candidates that minimize the number of the worst-case corner candidates mapped to the condition sets by handling the worst-case corner candidates thus mapped as a single worst-case corner candidate to be worst-case corners.Type: GrantFiled: August 16, 2011Date of Patent: April 9, 2013Assignee: Fujitsu LimitedInventors: Hiroyuki Higuchi, Hidetoshi Matsuoka
-
Publication number: 20120155196Abstract: A semiconductor memory includes a memory cell array that includes data cells of x bits and redundant cells of y bits for each word; a position-data storage unit that stores, for each word, defective-cell position data of defective cells of the data cells and the redundant cells; and a read circuit that reads data from cells of x bits based on the defective-cell position data stored in the position-data storage unit for a specified word of which address is specified as read address, the cells of x bits being formed by the data cells of x bits and the redundant cells of y bits of the specified word other than the defective cells.Type: ApplicationFiled: September 1, 2011Publication date: June 21, 2012Applicant: Fujitsu LimitedInventors: Yoshinori Tomita, Hidetoshi Matsuoka, Hiroyuki Higuchi