Patents by Inventor Hidetoshi Morishita

Hidetoshi Morishita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10291222
    Abstract: A gate potential control device configured to control potential of a gate of a main switching element is provided herein. The gate potential control device includes: a turn-on switching element and a turn-off switching element. In a turn-off operation, a main voltage between main terminals of the main switching element increases from an on-voltage to a peak value of a surge voltage and then decreases to an off-voltage. The gate potential control device is configured to keep both of the turn-on switching element and the turn-off switching element turned off in a period which is at least a part of a specific period in the turn-off operation, the specific period being from a timing after a predetermined time lapse from a timing of rise-up of the main voltage from the on-voltage to a timing at which the main voltage reaches the peak value.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 14, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidetoshi Morishita, Hikaru Watanabe
  • Publication number: 20180269870
    Abstract: A gate potential control device configured to control potential of a gate of a main switching element is provided herein. The gate potential control device includes: a turn-on switching element and a turn-off switching element. In a turn-off operation, a main voltage between main terminals of the main switching element increases from an on-voltage to a peak value of a surge voltage and then decreases to an off-voltage. The gate potential control device is configured to keep both of the turn-on switching element and the turn-off switching element turned off in a period which is at least a part of a specific period in the turn-off operation, the specific period being from a timing after a predetermined time lapse from a timing of rise-up of the main voltage from the on-voltage to a timing at which the main voltage reaches the peak value.
    Type: Application
    Filed: February 23, 2018
    Publication date: September 20, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidetoshi MORISHITA, Hikaru WATANABE
  • Patent number: 9330835
    Abstract: A signal transmitting apparatus using a plane coil for a sending coil and a receiving coil respectively, so that the outer diameters of the sending coil and the receiving coil can be decreased, and a signal can be stably transmitted from a sending side to a receiving side. The signal transmitting apparatus is provided with: a sending coil driven by an inputted signal; a receiving coil configured to output a received signal in response to the sending coil being driven; a pre-processing circuit to which the received signal outputted by the receiving coil is inputted; and a detecting circuit configured to detect the inputted signal from a signal outputted by the pre-processing circuit.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: May 3, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidetoshi Morishita, Masaki Wasekura
  • Patent number: 8638158
    Abstract: A signal transmitting apparatus that may suppress generation of a noise voltage attributable to a common mode voltage is provided. A transistor P1 is connected between a first terminal of a sending coil and a power supply voltage. A transistor N1 is connected between the first terminal and a ground voltage. A transistor P2 is connected between a second terminal of the sending coil and the power supply voltage. A transistor N2 is connected between the second terminal and the ground voltage. In a period-PE1 a coil current flowing in a positive direction is generated by turning on the transistors P1 and N2 and turning off the transistors P2 and N1, and then the transistor N1 is turned on in response to turning off the transistor P1. In a period PE2, a coil current flowing in a negative direction is generated by turning off the transistors P1 and N2 and turning on the transistors P2 and N1, and then the transistor N2 is turned on in response to turning off the transistor P2.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: January 28, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hidetoshi Morishita, Masaki Wasekura
  • Patent number: 8373251
    Abstract: A first semiconductor chip includes a first inductor and a second inductor, and a second semiconductor chip includes a third inductor and a fourth inductor. The first inductor is connected to a first receiving circuit of the first semiconductor chip, and the second inductor is connected to a second transmitting circuit of the second semiconductor chip through a first bonding wire. The third inductor is connected to a second receiving circuit of the second semiconductor chip, and the fourth inductor is connected to a first transmitting circuit of the first semiconductor chip through a second bonding wire.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: February 12, 2013
    Assignees: Renesas Electronics Corporation, Toyota Jidosha Kabushiki Kaisha
    Inventors: Shinichi Uchida, Masayuki Furumiya, Hiroshi Sakakibara, Takashi Iwadare, Yoshiyuki Sato, Makoto Eguchi, Masato Taki, Hidetoshi Morishita, Kozo Kato, Jun Morimoto
  • Publication number: 20130002040
    Abstract: The present application provides a technique for a signal transmitting apparatus using a plane coil for a sending coil and a receiving coil respectively, so that the outer diameters of the sending coil and the receiving coil can be decreased, and a signal can be stably transmitted from a sending side to a receiving side. The signal transmitting apparatus disclosed in the present application is provided with: a sending coil driven by an inputted signal; a receiving coil configured to output a received signal in response to the sending coil being driven; a pre-processing circuit to which the received signal outputted by the receiving coil is inputted; and a detecting circuit configured to detect the inputted signal from a signal outputted by the pre-processing circuit.
    Type: Application
    Filed: March 9, 2010
    Publication date: January 3, 2013
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidetoshi Morishita, Masaki Wasekura
  • Publication number: 20120319743
    Abstract: A signal transmitting apparatus that may suppress generation of a noise voltage attributable to a common mode voltage is provided. A transistor P1 is connected between a first terminal of a sending coil and a power supply voltage. A transistor N1 is connected between the first terminal and a ground voltage. A transistor P2 is connected between a second terminal of the sending coil wand the power supply voltage. A transistor N2 is connected between the second terminal and the ground voltage. In a period-PE1, a coil current flowing in a positive direction is generated by turning on the transistors P1 and N2 and turning off the transistors P2 and N1, and then the transistor N1 is turned on in response to turning off the transistor P1. In a period PE2, a coil current flowing in a negative direction is generated by turning off the transistors P1 and N2 and turning on the transistors P2 and N1, and then the transistor N2 is turned on in response to turning off the transistor P2.
    Type: Application
    Filed: February 1, 2010
    Publication date: December 20, 2012
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAIHSA
    Inventors: Hidetoshi Morishita, Masaki Wasekura
  • Publication number: 20100230782
    Abstract: A first semiconductor chip includes a first inductor and a second inductor, and a second semiconductor chip includes a third inductor and a fourth inductor. The first inductor is connected to a first receiving circuit of the first semiconductor chip, and the second inductor is connected to a second transmitting circuit of the second semiconductor chip through a first bonding wire. The third inductor is connected to a second receiving circuit of the second semiconductor chip, and the fourth inductor is connected to a first transmitting circuit of the first semiconductor chip through a second bonding wire.
    Type: Application
    Filed: March 10, 2010
    Publication date: September 16, 2010
    Applicants: NEC ELECTRONICS CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shinichi UCHIDA, Masayuki FURUMIYA, Hiroshi SAKAKIBARA, Takashi IWADARE, Yoshiyuki SATO, Makoto EGUCHI, Masato TAKI, Hidetoshi MORISHITA, Kozo KATO, Jun MORIMOTO
  • Patent number: 7746158
    Abstract: A driving device of an IGBT includes a high potential side switch device group having a plurality of switch devices and, one end of each switch device being connected to a high potential side; a low potential side switch device group having a plurality of switch devices and, one end of each switch device being connected to a low potential side; an drive type selective input terminal to which a drive type selection signal corresponding to drive type of the IGBT connected to the driving device is inputted; a direct drive type control unit and an indirect drive type control unit generating a control signal controlling complementarily the high potential side switch device group and the low potential side switch device group corresponding to the drive type of the IGBT; and a selector selecting the control signal controlling the high potential side switch device group and the low potential side switch device group corresponding to an inputted drive type selection signal.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: June 29, 2010
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hidetoshi Morishita, Hideo Yamawaki, Yuu Suzuki
  • Publication number: 20090021294
    Abstract: A driving device 10 of an IGBT 1 comprises a high potential side switch device group having a plurality of switch devices M1 and M1?, one of ends of each switch device being connected to a high potential side; a low potential side switch device group having a plurality of switch devices M2 and M2?, one of ends of each switch device being connected to a low potential side; an drive type selective input terminal 10b to which a drive type selection signal corresponding to drive type of the IGBT 1 connected to the driving device 10 is inputted; a direct drive type control unit 23 and an indirect drive type control unit 24 generating a control signal controlling complementarily the high potential side switch device group and the low potential side switch device group corresponding to the drive type of the IGBT 1; and a selector 25 selecting the control signal controlling the high potential side switch device group and the low potential side switch device group corresponding to an inputted drive type selection sign
    Type: Application
    Filed: May 2, 2006
    Publication date: January 22, 2009
    Inventors: Hidetoshi Morishita, Hideo Yamawaki, Yuu Suzuki
  • Patent number: 6402831
    Abstract: Concrete characterized by containing aqueous slurry of ground calcium carbonate which has a mean particle diameter of 0.5-3 micrometers produced by wet pulverization of the limestone. By adding fine powder of ground calcium carbonate, fluidity of the concrete is increased and workability thereof is improved.
    Type: Grant
    Filed: April 27, 2000
    Date of Patent: June 11, 2002
    Assignee: Fimatec, Ltd.
    Inventors: Haruya Sawara, Tadashi Yamauchi, Hidetoshi Morishita, Seiji Katayama, Yumiko Takase