Patents by Inventor Hidetoshi Murai

Hidetoshi Murai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150265939
    Abstract: An assembly toy includes a first component having cylindrical first connection sections formed at both ends thereof and a second component provided with a plurality of second connection sections which are detachably fitted and attached to the first connection sections. The second connection sections are provided such that end sections in a longitudinal direction are linked and other end sections protrude outward in the radial direction.
    Type: Application
    Filed: June 8, 2015
    Publication date: September 24, 2015
    Inventor: Hidetoshi MURAI
  • Patent number: 8436798
    Abstract: A method for driving an electro-optic device includes a first and second electrode and a pair of substrates sandwiching an electro-optic layer driven by the first electrode. The method involves shifting one of two potentials input to at least one of the electrodes such that a potential difference between the first and second electrode where the potential input to the first electrode is higher than the potential input to the second electrode is larger than a potential difference between the first and second electrode where the potential input to the first electrode is lower than the potential input to the second electrode, when a gray-scale level where potential input to the first electrode is higher than potential input to the second electrode is equivalent to the gray-scale level where potential input to the first electrode is lower than potential input to the second electrode.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: May 7, 2013
    Assignee: Sony Corporation
    Inventors: Hidetoshi Murai, Tomoaki Sekime, Hayato Kurasawa, Jin Ota
  • Patent number: 7787091
    Abstract: A transverse field type liquid crystal display panel has multiple scan lines 12 and common wires 13 provided in parallel, multiple signal lines 17 provided in the direction crossing the scan lines 12, and common electrodes 14 and pixel electrodes 21 formed in the regions delimited by the multiple scan lines 12 and signal lines 17. At least part of the surface of an insulator laid over the scan lines 17 is covered by shield electrodes 22 constituted of a conductive material. Thanks to such structure, there can be provided a transverse field type—that is, an IPS mode or FFS mode—liquid crystal display panel that is equipped with a device for preventing burn-in due to the voltage that is applied to the scan lines.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: August 31, 2010
    Assignee: Sony Corporation
    Inventors: Masahiro Horiguchi, Hideki Kaneko, Hidetoshi Murai, Hayato Kurasawa, Yasuo Segawa
  • Publication number: 20080284962
    Abstract: A transverse field type liquid crystal display panel has multiple scan lines 12 and common wires 13 provided in parallel, multiple signal lines 17 provided in the direction crossing the scan lines 12, and common electrodes 14 and pixel electrodes 21 formed in the regions delimited by the multiple scan lines 12 and signal lines 17. At least part of the surface of an insulator laid over the scan lines 17 is covered by shield electrodes 22 constituted of a conductive material. Thanks to such structure, there can be provided a transverse field type—that is, an IPS mode or FFS mode—liquid crystal display panel that is equipped with a device for preventing burn-in due to the voltage that is applied to the scan lines.
    Type: Application
    Filed: August 8, 2007
    Publication date: November 20, 2008
    Applicant: EPSON IMAGING DEVICES CORPORATION
    Inventors: Masahiro HORIGUCHI, Hideki KANEKO, Hidetoshi MURAI, Hayato KURASAWA, Yasuo SEGAWA
  • Publication number: 20080218462
    Abstract: A method for diving an electro-optic device including a pair of substrates sandwiching an electro-optic layer, and first and second electrodes disposed on one of the pair of substrates, the first electrode being used to drive the electro-optic layer, the second electrode being disposed closer to the electro-optic layer than the first electrode.
    Type: Application
    Filed: December 12, 2007
    Publication date: September 11, 2008
    Applicant: EPSON IMAGING DEVICES CORPORATION
    Inventors: Hidetoshi Murai, Tomoaki Sekime, Hayato Kurasawa, Jin Ota
  • Patent number: 7182877
    Abstract: A method is provided for manufacturing an electro-optical device, in which fine scratches or cracks can be removed by etching without damaging wiring, an electro-optical device, and an electronic apparatus. According to the method, a liquid crystal panel used in an electro-optical device is cut as a single product. Then, before an IC mounting step, in a state of the single product liquid crystal panel, a wet etching is performed on the cut faces and edges of the first and second substrates to remove fine scratches or cracks from the cut faces and edges of the substrates. At this time, wiring portions, IC mounting terminals, substrate mounting terminals, and alignment marks, which are formed on the protruding region, are covered with a protection layer.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: February 27, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Hidetoshi Murai, Manabu Hanakawa
  • Publication number: 20040182817
    Abstract: A method is provided for manufacturing an electro-optical device, in which fine scratches or cracks can be removed by etching without damaging wiring, an electro-optical device, and an electronic apparatus. According to the method, a liquid crystal panel used in an electro-optical device is cut as a single product. Then, before an IC mounting step, in a state of the single product liquid crystal panel, a wet etching is performed on the cut faces and edges of the first and second substrates to remove fine scratches or cracks from the cut faces and edges of the substrates. At this time, wiring portions, IC mounting terminals, substrate mounting terminals, and alignment marks, which are formed on the protruding region, are covered with a protection layer.
    Type: Application
    Filed: December 10, 2003
    Publication date: September 23, 2004
    Inventors: Hidetoshi Murai, Manabu Hanakawa