Patents by Inventor Hidetoshi Nishikawa

Hidetoshi Nishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200038459
    Abstract: The present invention provides a composition for preventing or treating a graft-versus-host disease, the composition comprising a fecal microbiota.
    Type: Application
    Filed: October 14, 2019
    Publication date: February 6, 2020
    Inventors: Kazuhiko Kakihana, Masahira HATTORI, Kenya HONDA, Hiroyoshi NISHIKAWA, Hidetoshi MORITA, Kozue TAKESHITA
  • Patent number: 10427828
    Abstract: A corrugated paperboard box is provided in which when flaps are bent, a perforated line along which the flaps can be separated from the box is less likely to break. Such a corrugated paperboard box includes a peripheral wall and top flaps, and is formed, at the boundary area between the peripheral wall and the top flaps, with a groove-shaped reverse scoreline recessed on the side of an outer linerboard, and a pair of groove-shaped recesses recessed on the side of an inner linerboard, and extending in parallel to each other so as to sandwich the area in which the reverse scoreline extends. The corrugated paperboard box is further formed, in one of the groove-shaped recesses, with a perforated line along which the top flaps can be separated from the peripheral wall. The top flaps can be bent along the perforated line toward the inner surface of the peripheral wall.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: October 1, 2019
    Assignee: RENGO CO., LTD.
    Inventors: Taishi Yamada, Takashi Kajizuka, Hidetoshi Tonooka, Eiji Yamahara, Hiromu Ikeda, Taku Furuta, Atsuo Ishikawa, Katsuhiko Yasumoto, Satoshi Mochizuki, Yoichi Nishikawa, Masayoshi Ootani
  • Patent number: 10357942
    Abstract: A graphite-silicon composite, including: graphite; silicon; and an intermediate layer that is located between the graphite and the silicon, wherein the intermediate layer includes oxygen, carbon and silicon. Furthermore, provided is a method for producing a graphite-silicon composite, including: layering graphite and silicon; and heating the layered graphite and silicon while applying pressure to them, wherein, during heating the layered graphite and silicon while applying pressure to them, an oxygen concentration in the atmosphere is adjusted to 0.2 vol %, the applied pressure is adjusted to 24.5 MPa or higher, and the heating temperature is adjusted to 1260° C. or higher.
    Type: Grant
    Filed: July 9, 2016
    Date of Patent: July 23, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kazuhiro Nishikawa, Naomi Nishiki, Hidetoshi Kitaura, Atsushi Tanaka, Kimiaki Nakaya, Henrik Rønnow
  • Patent number: 8502526
    Abstract: A magnetic sensor circuit of the present invention includes: a Hall device 10; selection switch circuit 20 switching a detection state of the Hall device 10 to either a first switch state or a second switch state; a comparator unit 60 performing comparison using a detection voltage of a magnetoelectric conversion device 10 aid a predetermined reference voltage to generate a comparison result signal COUT; a logic circuit 80 generating, based on an output signal OUT and the comparison result signal COUT, a logic operation signal LOUT for maintaining or inverting the logic of the output signal OUT; a latch circuit 70 latching the logic operation signal LOUT to output this as the output signal OUT; and a control circuit go determining, based on the output signal OUT, an order of switching the detection state of the Hall device 10 (from the first switch state to the second switch state, or from the second switch state to the first switch state).
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: August 6, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Hidetoshi Nishikawa
  • Patent number: 7701208
    Abstract: A Hall element outputs a Hall voltage generated at a first terminal pair or a second terminal pair to first and second output terminals by switching the voltage in a first status and a second status. Based on the voltages of the first and the second output terminals and a reference voltage, first and second capacitors are charged. Then, the voltages of the first and the second capacitors are compared, and a detection signal is obtained. Thus, a magnetic sensor circuit which reduces influence of an element offset voltage of the Hall element and also reduces influence of an input offset voltage generated at an amplifier, and a portable terminal provided with such magnetic sensor circuit are provided.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: April 20, 2010
    Assignee: Rohm Co., Ltd.
    Inventor: Hidetoshi Nishikawa
  • Patent number: 7659716
    Abstract: A sensor circuit has: a sensor portion that obtains, as an electrical signal, information on an object to be measured or detected; and a control circuit that controls the operation of the sensor portion. The control circuit receives a start input signal inputted thereto from outside for making the sensor portion operate only for a given duration after the start input signal is inputted thereto. With this configuration, it is possible to reduce the current consumption by arbitrarily controlling a period of an intermittent operation of the sensor circuit.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: February 9, 2010
    Assignee: Rohm Co., Ltd.
    Inventor: Hidetoshi Nishikawa
  • Publication number: 20100026281
    Abstract: A magnetic sensor circuit of the present invention includes: a Hall device 10; selection switch circuit 20 switching a detection state of the Hall device 10 to either a first switch state or a second switch state; a comparator unit 60 performing comparison using a detection voltage of a magnetoelectric conversion device 10 aid a predetermined reference voltage to generate a comparison result signal COUT; a logic circuit 80 generating, based on an output signal OUT and the comparison result signal COUT, a logic operation signal LOUT for maintaining or inverting the logic of the output signal OUT; a latch circuit 70 latching the logic operation signal LOUT to output this as the output signal OUT; and a control circuit go determining, based on the output signal OUT, an order of switching the detection state of the Hall device 10 (from the first switch state to the second switch state, or from the second switch state to the first switch state).
    Type: Application
    Filed: June 20, 2008
    Publication date: February 4, 2010
    Applicant: Rohm Co., Ltd.
    Inventor: Hidetoshi Nishikawa
  • Patent number: 7514963
    Abstract: When the operation frequency is high, in order to cause the rate of change of outputs from an output terminal (OUT) to be abrupt, a selection control signal is caused to be in a low state, thereby causing MOS transistors (T5b, T6b) to be in ON states, thereby causing the combined resistance of the ON-resistances of the MOS resistors in a NOR gate (NOx) to be small. On the other hand, when the operation frequency is low, in order to cause the rate of change of outputs from the output terminal (OUT) to be gentle, the selection control signal is caused to be in a high state, thereby causing the MOS transistors (T5b, T6b) to be in OFF states, thereby causing the combined resistance of the ON-resistances of the MOS transistors in the NOR gate (NOx) to be large.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: April 7, 2009
    Assignee: Rohm Co., Ltd.
    Inventor: Hidetoshi Nishikawa
  • Publication number: 20080265880
    Abstract: A Hall element (10) outputs a Hall voltage generated at a first terminal pair (A, C) or a second terminal pair (B, D) to first and second output terminals by switching the voltage in a first status and a second status. Based on the voltages of the first and the second output terminals and a reference voltage, first and second capacitors (41, 42) are charged. Then, the voltages of the first and the second capacitors (41, 42) are compared, and a detection signal is obtained. Thus, a magnetic sensor circuit (1) which reduces influence of an element offset voltage of the Hall element (10) and also reduces influence of an input offset voltage generated at an amplifier (30), and a portable terminal provided with such magnetic sensor circuit (1) are provided.
    Type: Application
    Filed: February 6, 2006
    Publication date: October 30, 2008
    Applicant: ROHM CO., LTD.
    Inventor: Hidetoshi Nishikawa
  • Publication number: 20080048772
    Abstract: A sensor circuit has: a sensor portion that obtains, as an electrical signal, information on an object to be measured or detected; and a control circuit that controls the operation of the sensor portion. The control circuit receives a start input signal inputted thereto from outside for making the sensor portion operate only for a given duration after the start input signal is inputted thereto. With this configuration, it is possible to reduce the current consumption by arbitrarily controlling a period of an intermittent operation of the sensor circuit.
    Type: Application
    Filed: July 25, 2007
    Publication date: February 28, 2008
    Applicant: ROHM CO., LTD.
    Inventor: Hidetoshi Nishikawa
  • Publication number: 20080030191
    Abstract: A magnetic sensor circuit has Hall devices 10X and 10Y, selection switch circuits 20X and 20Y, amplifier units 30X ad 30Y, a comparison unit 60, capacitors 41X, 42X, 41Y, and 42Y, and switch circuits 51 and 52. The Hall voltages obtained from the Hall devices 10X and 10Y are outputted in either of a first and a second states switched by the selection switch circuits 20X and 20Y. The amplifier units 30X ad 30Y each operate differentially and, if the difference between their outputs is greater than a set hysteresis width, the output logic of a detection signal Sdet is shifted. This configuration helps reduce the influence of device offset voltages in the Hall devices, and also helps reduce the influence of input offset voltages arising in the amplifiers.
    Type: Application
    Filed: July 25, 2007
    Publication date: February 7, 2008
    Applicant: ROHM CO., LTD.
    Inventor: Hidetoshi Nishikawa
  • Publication number: 20080013962
    Abstract: According to the invention, a pulse-modulated signal demodulation circuit has a first integration circuit, a second integration circuit, and a third integration circuit. The first integration circuit generates a first pulse signal containing a pulse having a pulse width corresponding to the number of any consecutive pulses in the pulse-modulated signal. The second integration circuit generates a second pulse signal by removing from the first pulse signal any pulse independent of any other pulse and having a pulse width smaller than or equal to a predetermined pulse width, then producing a pulse corresponding to the pulse width of any pulse in the first pulse signal that is independent of any other pulse and has a pulse width greater than the predetermined pulse width, and then coupling together any pulse in the first pulse signal that is non-independent and thereby producing a pulse corresponding to the pulse width of the non-independent pulse.
    Type: Application
    Filed: July 5, 2005
    Publication date: January 17, 2008
    Inventor: Hidetoshi Nishikawa
  • Publication number: 20070285155
    Abstract: A discrimination circuit of the present invention checks whether a received signal is noise or a signal that is repeated with interposed rest time periods, and is provided with a low-pass filter that has a cut-off frequency that is lower than the frequency of the noise but higher than the reciprocal of a total period of one frame of the signal that is repeated with interposed rest time periods and the rest time period, and a judgment circuit that judges, according to an output of the low-pass filter, whether the received signal is noise or a signal that is repeated with interposed rest time periods. With this configuration, it is possible to discriminate between noise and a signal that is repeated with interposed rest time periods, and achieve miniaturization.
    Type: Application
    Filed: July 11, 2005
    Publication date: December 13, 2007
    Inventors: Shinji Yano, Hidetoshi Nishikawa
  • Patent number: 7256618
    Abstract: A semiconductor integrated circuit device (1) includes: a transistor switch (SWA) for electrically connecting and disconnecting output of a flip-flop (FF64) of a shift register (SR1) and input of a flip-flop (FF65) of a shift register (SR2); and a transistor switch (SWB) for electrically connecting and disconnecting an input driver (Din2) and input of the flip-flop (FF65). Here, when the shift registers (SR1 and SR2) are connected, the transistor switch (SWA) is turned ON and the transistor switch (SWB) is turned OFF by a selection signal.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: August 14, 2007
    Assignee: Rohm Co., Ltd.
    Inventor: Hidetoshi Nishikawa
  • Publication number: 20060232299
    Abstract: A semiconductor integrated circuit device (1) includes: a transistor switch (SWA) for electrically connecting and disconnecting output of a flip-flop (FF64) of a shift register (SR1) and input of a flip-flop (FF65) of a shift register (SR2); and a transistor switch (SWB) for electrically connecting and disconnecting an input driver (Din2) and input of the flip-flop (FF65). Here, when the shift registers (SR1 and SR2) are connected, the transistor switch (SWA) is turned ON and the transistor switch (SWB) is turned OFF by a selection signal.
    Type: Application
    Filed: July 15, 2004
    Publication date: October 19, 2006
    Inventor: Hidetoshi Nishikawa
  • Patent number: 7086727
    Abstract: A heat fixing apparatus has a heating unit for heating a recording medium having a substrate, a fixing layer and a surface layer so as to sublimate sublimating ink applied in advance to the surface layer for transferring the sublimated ink to the fixing layer. The heating unit includes a heating transporting mechanism for transporting the recording medium within a heating space, a heater body for heating air, and a blower mechanism for supplying hot air heated by the heater body to the recording medium being transported by the heating transporting mechanism. The apparatus further includes a flat guide member for coming into contact with the surface of the recording medium being transported by the heating transporting mechanism and a heater for heating the guide member.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: August 8, 2006
    Assignee: Noritsu Koki Co., Ltd.
    Inventors: Hidetoshi Nishikawa, Kazunobu Shima, Masazumi Ishikawa, Kazuo Nagaosa, Masaki Nakamoto, Masanori Inoshita, Masasuke Funase, Toshihiro Matsuoka
  • Publication number: 20060158921
    Abstract: When the operation frequency is high, in order to cause the rate of change of outputs from an output terminal (OUT) to be abrupt, a selection control signal is caused to be in a low state, thereby causing MOS transistors (T5b, T6b) to be in ON states, thereby causing the combined resistance of the ON-resistances of the MOS resistors in a NOR gate (NOx) to be small. On the other hand, when the operation frequency is low, in order to cause the rate of change of outputs from the output terminal (OUT) to be gentle, the selection control signal is caused to be in a high state, thereby causing the MOS transistors (T5b, T6b) to be in OFF states, thereby causing the combined resistance of the ON-resistances of the MOS transistors in the NOR gate (NOx) to be large.
    Type: Application
    Filed: June 21, 2004
    Publication date: July 20, 2006
    Inventor: Hidetoshi Nishikawa
  • Patent number: 6953969
    Abstract: In a conventional N-channel MOSFET for an open-drain circuit, when a positive static electric charge is applied to its drain, there is no route by way of which to discharge the static electric charge, resulting in a rather low static withstand voltage. To overcome this, according to the invention, an open-drain N-channel MOSFET has a drain region formed of an N-type semiconductor layer, a P-type impurity diffusion layer formed within the drain region, two high-concentration N-type impurity diffusion layers formed within the drain region so as to sandwich the P-type impurity diffusion layer, and a drain electrode connected to the P-type impurity diffusion layer and to the two high-concentration N-type impurity diffusion layers. When a positive static electric charge is applied to the drain, a parasitic transistor appears that forms a route by way of which the static electric charge is discharged.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: October 11, 2005
    Assignee: Rohm Co., Ltd.
    Inventors: Hidetoshi Nishikawa, Masahiko Sonoda
  • Publication number: 20050218457
    Abstract: In a conventional N-channel MOSFET for an open-drain circuit, when a positive static electric charge is applied to its drain, there is no route by way of which to discharge the static electric charge, resulting in a rather low static withstand voltage. To overcome this, according to the invention, an open-drain N-channel MOSFET has a drain region formed of an N-type semiconductor layer, a P-type impurity diffusion layer formed within the drain region, two high-concentration N-type impurity diffusion layers formed within the drain region so as to sandwich the P-type impurity diffusion layer, and a drain electrode connected to the P-type impurity diffusion layer and to the two high-concentration N-type impurity diffusion layers. When a positive static electric charge is applied to the drain, a parasitic transistor appears that forms a route by way of which the static electric charge is discharged.
    Type: Application
    Filed: May 24, 2005
    Publication date: October 6, 2005
    Inventors: Hidetoshi Nishikawa, Masahiko Sonoda
  • Patent number: 6893122
    Abstract: An image forming apparatus for forming an image on a recording medium by heating the medium having ink applied to its surface layer by a heater device, thereby to fix the ink applied to the surface layer to a fixing layer of the recording medium. A heating controlling section (78) for controlling the heater device (4) includes a fixing behavior evaluating means (9) for evaluating a fixing behavior of the ink to the fixing layer and then outputting a control amount to the heating controlling section (78) for controlling the heater device (4). The fixing behavior evaluating means (9) includes such functions as a sublimation degree evaluating function for evaluating a sublimation degree of the ink in the recording medium (1), a function for evaluating surface temperature distribution of the recording medium or a transferred energy evaluating function for evaluating transferred energy received by each area of the recording medium (1).
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: May 17, 2005
    Assignee: Noritsu Koki Co., Ltd.
    Inventors: Kazunobu Shima, Hidetoshi Nishikawa, Masazumi Ishikawa