Patents by Inventor Hidetoshi Ohnuma

Hidetoshi Ohnuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8221942
    Abstract: A pattern correction method includes: a correction step of performing pattern correction on a semiconductor circuit pattern having plural transistors as component elements; an order of priority recognition step of recognizing an order of priority set with respect to the plural transistors prior to the pattern correction at the correction step; and a condition adjustment step of adjusting correction conditions for the pattern correction with reference to the transistor having a high priority recognized at the order of priority recognition step in the pattern correction at the correction step.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: July 17, 2012
    Assignee: Sony Corporation
    Inventors: Mikio Oka, Kaoru Koike, Kensuke Tsuchiya, Hidetoshi Ohnuma
  • Publication number: 20100183960
    Abstract: A pattern correction method includes: a correction step of performing pattern correction on a semiconductor circuit pattern having plural transistors as component elements; an order of priority recognition step of recognizing an order of priority set with respect to the plural transistors prior to the pattern correction at the correction step; and a condition adjustment step of adjusting correction conditions for the pattern correction with reference to the transistor having a high priority recognized at the order of priority recognition step in the pattern correction at the correction step.
    Type: Application
    Filed: January 15, 2010
    Publication date: July 22, 2010
    Applicant: SONY CORPORATION
    Inventors: Mikio Oka, Kaoru Koike, Kensuke Tsuchiya, Hidetoshi Ohnuma
  • Patent number: 7200834
    Abstract: Disclosed is an exposure pattern forming method of forming an exposure pattern by correcting each pattern portion constituting a design pattern by a correction amount, which amount is previously prepared so as to correspond to both a line width of the pattern portion and a space width of a space portion adjacent to the pattern portion, characterized by including the steps of: subjecting the design pattern to graphic form arithmetic operation, to extract each pattern portion for each target line width, and to extract space portion for each target space width; and subjecting each pattern portion extracted for each target line width and the space portion extracted for each target space width to graphic form arithmetic operation based on the corresponding one of the correction amounts, to thereby correct the pattern portion having each target line width for each target space width.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: April 3, 2007
    Assignee: Sony Corporation
    Inventors: Kazuhisa Ogawa, Hidetoshi Ohnuma
  • Patent number: 7165235
    Abstract: The present invention provides an exposure pattern forming method using a rule-based proximity effect correction method to which graphic form arithmetic operation is applied.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: January 16, 2007
    Assignee: Sony Corporation
    Inventors: Kazuhisa Ogawa, Hidetoshi Ohnuma
  • Patent number: 7139996
    Abstract: By correcting an optical proximity effect with respect to design patterns by an optical proximity effect correcting means and simulating patterns after the correction of optical proximity effect by a simulation means, transfer patterns of gate electrodes are generated and measurement portion in the transfer patterns of the gate electrodes are changed in accordance with characteristics required for a circuit. Then, in accordance with whether the point required from the circuit is a higher speed, stability, or a reduction of a leakage current, it is judged whether or not a deviation from the design value at the measurement point of the transfer pattern of the gate electrode as explained above is within an allowable range. The pattern of the measurement point is shifted when the deviation is not within the allowable range.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: November 21, 2006
    Assignee: Sony Corporation
    Inventors: Hidetoshi Ohnuma, Kazuyoshi Kawahara
  • Patent number: 7000216
    Abstract: The present invention provides an exposure pattern forming method using a rule-based proximity effect correction method to which graphic form arithmetic operation is applied.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: February 14, 2006
    Assignee: Sony Corporation
    Inventors: Kazuhisa Ogawa, Hidetoshi Ohnuma
  • Publication number: 20060008712
    Abstract: A pair of reflective masks is provided in a photolithography process, wherein pattern forming elements are divided into respective directions relative to a projection vector of an EUV ray, so that each of the reflective masks has the same pattern forming elements extending in one direction. The exposure process is carried out sequentailly to an object to be exposed using respective reflective masks, and when a reflection mask is changed from one to the other, the object and the other reflective mask are rotated so that the angle of the object and the projection vector becomes the same angle with the reflective mask before it is changed.
    Type: Application
    Filed: September 14, 2005
    Publication date: January 12, 2006
    Inventor: Hidetoshi Ohnuma
  • Publication number: 20050204330
    Abstract: Disclosed is an exposure pattern forming method of forming an exposure pattern by correcting each pattern portion constituting a design pattern by a correction amount, which amount is previously prepared so as to correspond to both a line width of the pattern portion and a space width of a space portion adjacent to the pattern portion, characterized by including the steps of: subjecting the design pattern to graphic form arithmetic operation, to extract each pattern portion for each target line width, and to extract space portion for each target space width; and subjecting each pattern portion extracted for each target line width and the space portion extracted for each target space width to graphic form arithmetic operation based on the corresponding one of the correction amounts, to thereby correct the pattern portion having each target line width for each target space width.
    Type: Application
    Filed: March 2, 2005
    Publication date: September 15, 2005
    Inventors: Kazuhisa Ogawa, Hidetoshi Ohnuma
  • Publication number: 20050174557
    Abstract: The present invention provides an exposure pattern forming method using a rule-based proximity effect correction method to which graphic form arithmetic operation is applied.
    Type: Application
    Filed: April 8, 2005
    Publication date: August 11, 2005
    Inventors: Kazuhisa Ogawa, Hidetoshi Ohnuma
  • Patent number: 6928636
    Abstract: A rule-based OPC evaluating method and a simulation-based OPC model evaluating method for accurately evaluating line width controllability are disclosed. Mask pattern design data about an evaluation-use mask are input to rule-based OPC to obtain correction data about the mask pattern on the evaluation-use mask. An evaluation-use wafer is fabricated based on the correction data thus acquired. Gate patterns on the evaluation-use wafer are measured for size. Based on a simulation-based OPC model having undergone process calibration, simulation data are output corresponding to all gate patterns on the evaluation-use wafer. The measured data about the evaluation-use gate patterns are compared with the simulation data, whereby the rule-based OPC is evaluated.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: August 9, 2005
    Assignee: Sony Corporation
    Inventor: Hidetoshi Ohnuma
  • Patent number: 6924068
    Abstract: The present invention is a method capable of fabricating photomasks with improved control of gate line width wafers. More specifically a method is provided to determine a mask correction unit 3 based on pattern space dependency 7 in the pattern obtained in the photolithographic process and etching process, and correct the mask fabrication design data 1 utilizing the mask correction unit 3, and fabricate photomasks using photolithographic equipment.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: August 2, 2005
    Assignee: Sony Corporation
    Inventor: Hidetoshi Ohnuma
  • Publication number: 20040073885
    Abstract: By correcting an optical proximity effect with respect to design patterns by an optical proximity effect correcting means and simulating patterns after the correction of optical proximity effect by a simulation means, transfer patterns of gate electrodes are generated and measurement portion in the transfer patterns of the gate electrodes are changed in accordance with characteristics required for a circuit. Then, in accordance with whether the point required from the circuit is a higher speed, stability, or a reduction of a leakage current, it is judged whether or not a deviation from the design value at the measurement point of the transfer pattern of the gate electrode as explained above is within an allowable range. The pattern of the measurement point is shifted when the deviation is not within the allowable range.
    Type: Application
    Filed: August 18, 2003
    Publication date: April 15, 2004
    Inventors: Hidetoshi Ohnuma, Kazuyoshi Kawahara
  • Publication number: 20040029024
    Abstract: A pair of reflective masks is provided in a photolithography process, wherein pattern forming elements are divided into respective direction relative to a projection vector of an EUV ray, so that each of the reflective masks has the same pattern forming elements extending in one direction. The exposure process is sequentially carried out to an object to be exposed using respective reflective mask, and when the reflection mask is changed from one to the other, the object and the other reflective mask are rotated so that the angle of the object and the projection vector becomes the same angle with the reflective mask before it is changed.
    Type: Application
    Filed: June 26, 2003
    Publication date: February 12, 2004
    Inventor: Hidetoshi Ohnuma
  • Publication number: 20030177467
    Abstract: A method of producing an OPC mask capable of suppressing the dispersion of the line width of a pattern actually formed on a wafer by performing a simulation with the influences of space dependency faithfully reflected thereon, the OPC mask, and a chip are provided. Measured data on a novel test pattern for a test mask is measured for the line width of each gate pattern. Simulation computation is conducted based on the measured data and design data of the novel test pattern, and simulation data of the novel test pattern deformed in shape by the optical proximity effect is outputted. When simulation accuracy is acceptable, a kernel is generated. Simulation is conducted by use of the kernel.
    Type: Application
    Filed: December 13, 2002
    Publication date: September 18, 2003
    Inventors: Hidetoshi Ohnuma, Chie Niikura
  • Publication number: 20030149955
    Abstract: A rule-based OPC evaluating method and a simulation-based OPC model evaluating method for accurately evaluating line width controllability are disclosed. Mask pattern design data about an evaluation-use mask are input to rule-based OPC to obtain correction data about the mask pattern on the evaluation-use mask. An evaluation-use wafer is fabricated based on the correction data thus acquired. Gate patterns on the evaluation-use wafer are measured for size. Based on a simulation-based OPC model having undergone process calibration, simulation data are output corresponding to all gate patterns on the evaluation-use wafer. The measured data about the evaluation-use gate patterns are compared with the simulation data, whereby the rule-based OPC is evaluated.
    Type: Application
    Filed: January 10, 2003
    Publication date: August 7, 2003
    Inventor: Hidetoshi Ohnuma
  • Publication number: 20030140329
    Abstract: The present invention provides an exposure pattern forming method using a rule-based proximity effect correction method to which graphic form arithmetic operation is applied.
    Type: Application
    Filed: December 3, 2002
    Publication date: July 24, 2003
    Inventors: Kazuhisa Ogawa, Hidetoshi Ohnuma
  • Patent number: 6492078
    Abstract: The present invention provides a correcting method of exposure pattern, an exposure method, a exposure system, a photomask and a semiconductor device, which can simplify an operation required for correcting an optical proximity effect of a light shielding film pattern and data processing. A serif pattern (37) relative to a light shielding film pattern (35) constituting a layout-designed exposure pattern (1) is prepared, and the light shielding film pattern (35) and the serif pattern (37) is graphically computed so as to correct the light shielding film pattern (35). An optical proximity effect in exposure is corrected by using the light shielding film pattern (35), and thereby, it is possible to simplify operational processing required for making an optical proximity effect correction with respect to the light shielding film pattern (35), and to considerably shorten a processing time for making the optical proximity effect correction.
    Type: Grant
    Filed: February 16, 2000
    Date of Patent: December 10, 2002
    Assignee: Sony Corporation
    Inventor: Hidetoshi Ohnuma
  • Patent number: 6391501
    Abstract: A mask pattern generating method and pattern generating apparatus capable of automatically arranging phase shifters efficiently without any discrepancies and to correct a line width difference caused by different densities of fine patterns; wherein shapes and phases of a plurality of phase shift patterns are determined based on positional relationships of a plurality of fine patterns, and the phases are determined so as to give a phase difference of the two sides of the fine patterns of 180 degrees. For example, a plurality of fine patterns are extracted from already designed element shape patterns, unit patterns of at least a predetermined width required for canceling light interference are arranged at the two sides in the direction of fine line width for each of the extracted plurality of the fine patterns, and a plurality of phase shift patterns are generated by OR processing of the unit patterns etc.
    Type: Grant
    Filed: January 22, 1999
    Date of Patent: May 21, 2002
    Assignee: Sony Corporation
    Inventor: Hidetoshi Ohnuma
  • Publication number: 20020045110
    Abstract: The present invention is a method capable of fabricating photomasks with improved control of gate line width wafers. More specifically a method is provided to determine a mask correction unit 3 based on pattern space dependency 7 in the pattern obtained in the photolithographic process and etching process, and correct the mask fabrication design data 1 utilizing the mask correction unit 3, and fabricate photomasks using photolithographic equipment.
    Type: Application
    Filed: October 17, 2001
    Publication date: April 18, 2002
    Applicant: Sony Corporation
    Inventor: Hidetoshi Ohnuma
  • Patent number: 6370441
    Abstract: A method for correcting designed-pattern data obtained by data-processing a plurality of designed patterns, comprising the steps of (a) producing hierarchical-area-bitmapped bitmap data from a plurality of the designed-pattern data, (b) determining a line width of the designed pattern and a space width between said designed pattern and a designed pattern adjacent to said designed pattern, from said hierarchical-area-bitmapped bitmap data, and (c) correcting the designed-pattern data on the basis of the determined line width and the determined space width, for proximity effect correction and/or optical proximity effect correction.
    Type: Grant
    Filed: April 8, 1998
    Date of Patent: April 9, 2002
    Assignee: Sony Corporation
    Inventor: Hidetoshi Ohnuma