Abstract: A semiconductor device capable of stabilizing an internal voltage is provided. According to one embodiment, the semiconductor device comprises a stabilized power supply circuit for generating a first voltage, a charge pump circuit for generating a second voltage different from the first voltage using the first voltage, the COUT2 including a comparison circuit for comparing the second voltage with a reference voltage, and a dummy load circuit controlled to be turned on or off in response to a comparison result signal COUT2 outputted from the comparison circuit, and the Dummy load circuit receives the comparison result signal COUT2 and is turned on for a predetermined period, whereby at least a part of a current IDD based on the first voltage flows into the dummy load circuit.

Abstract: A semiconductor device capable of stabilizing an internal voltage is provided. According to one embodiment, the semiconductor device comprises a stabilized power supply circuit for generating a first voltage, a charge pump circuit for generating a second voltage different from the first voltage using the first voltage, the COUT2 including a comparison circuit for comparing the second voltage with a reference voltage, and a dummy load circuit controlled to be turned on or off in response to a comparison result signal COUT2 outputted from the comparison circuit, and the Dummy load circuit receives the comparison result signal COUT2 and is turned on for a predetermined period, whereby at least a part of a current IDD based on the first voltage flows into the dummy load circuit.

Abstract: To improve reading accuracy of a sense amplifier circuit and a semiconductor memory device. A sense amplifier circuit includes an N type FET which is a sensing transistor connected between a power supply and a ground via a data line that extends to a memory cell, a resistance element that is connected between a gate of the sensing transistor and the power supply, and a capacitance element that is connected between the gate of the sensing transistor and the ground.

Abstract: To improve reading accuracy of a sense amplifier circuit and a semiconductor memory device. A sense amplifier circuit includes an N type FET which is a sensing transistor connected between a power supply and a ground via a data line that extends to a memory cell, a resistance element that is connected between a gate of the sensing transistor and the power supply, and a capacitance element that is connected between the gate of the sensing transistor and the ground.

Abstract: To improve reading accuracy of a sense amplifier circuit and a semiconductor memory device. A sense amplifier circuit includes an N type FET which is a sensing transistor connected between a power supply and a ground via a data line that extends to a memory cell, a resistance element that is connected between a gate of the sensing transistor and the power supply, and a capacitance element that is connected between the gate of the sensing transistor and the ground.

Abstract: A voltage generator for nonvolatile memory that generates an applied voltage to be applied to a nonvolatile memory includes a first voltage generator to generate a first voltage corresponding to the applied voltage, a reference voltage generator to generate a reference voltage, a comparator to compare the first voltage with the reference voltage and output a boost operation control signal according to a comparison result, and a booster to generate the applied voltage in a pulse-like voltage waveform by starting or stopping boost operation based on the boost operation control signal. The applied voltage corresponding to the first voltage upon inversion of the boost operation control signal is varied within one pulse-like voltage waveform by varying one of the first voltage and the reference voltage.

Abstract: A voltage generator for nonvolatile memory that generates an applied voltage to be applied to a nonvolatile memory includes a first voltage generator to generate a first voltage corresponding to the applied voltage, a reference voltage generator to generate a reference voltage, a comparator to compare the first voltage with the reference voltage and output a boost operation control signal according to a comparison result, and a booster to generate the applied voltage in a pulse-like voltage waveform by starting or stopping boost operation based on the boost operation control signal. The applied voltage corresponding to the first voltage upon inversion of the boost operation control signal is varied within one pulse-like voltage waveform by varying one of the first voltage and the reference voltage.

Abstract: A reference voltage circuit includes three PMOS transistors and two NMOS transistors. The three PMOS transistors constitute a current mirror circuit and the two NMOS transistors constitute a load circuit. A dummy NMOS transistor is added to the load circuit so as to make three NMOS transistors correspond to the three PMOS transistors and a ratio of currents leaking through PN junctions of diffusion layers on the side of the current mirror circuit is set equal to a ratio of currents leaking through PN junctions of diffusion layers on the side of the load circuit. This allows the reference voltage circuit to output a reference voltage that does not change with temperature even at high temperatures.

Abstract: A reference voltage circuit includes three PMOS transistors and two NMOS transistors. The three PMOS transistors constitute a current mirror circuit and the two NMOS transistors constitute a load circuit. A dummy NMOS transistor is added to a load circuit so as to make three NMOS transistors correspond to the three PMOS transistors and a ratio of currents leaking through PN junctions of diffusion layers on the side of the current mirror circuit is set equal to a ratio of currents leaking through PN junctions of diffusion layers on the side of the load circuit. This allows the reference voltage circuit to output a reference voltage that does not change with temperature even at high temperatures.

Abstract: A flash memory includes a programming section for programming one or more of memory cells at a time. The output node of the undoped programming transistor in the programming section is maintained at substantially constant irrespective of the number of the cell transistors being programmed at a time. The programming section has a voltage follower scheme including a differential amplifier and the programming transistor.

Abstract: A constant-voltage circuit has a differential amplifier circuit and an output stage circuit. The differential amplifier circuit is supplied with a predetermined reference voltage and produces an amplifier voltage in accordance with the predetermined reference voltage. The output stage circuit has a circuit output terminal and outputs an output voltage from the circuit output terminal in response to the amplifier voltage. The constant-voltage circuit further comprises an overshoot preventing section and a supplying section. The supplying section supplies a control signal to the overshoot preventing section when the source voltage is supplied to the constant-voltage circuit. The overshoot preventing section prevents the overshoot at the circuit output terminal in response to the control signal to control the output voltage to the predetermined constant voltage.