Patents by Inventor Hidetoshi Sugiyama

Hidetoshi Sugiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220276278
    Abstract: Means for determining whether or not a reagent necessary for a chemical reaction is normally discharged is provided for a liquid dispensing device that dispenses the reagent for the reaction. A liquid dispensing device as such means includes a temperature controller that controls a temperature of a reaction position to any appropriate temperature and a temperature monitor part that monitors the temperature of the reaction position, monitors with the temperature monitor part a change in the temperature of the reaction position when the dispensing device discharges a reagent, and when a temperature change amount deviates from a beforehand determined threshold range, determines abnormal dispensation.
    Type: Application
    Filed: February 21, 2020
    Publication date: September 1, 2022
    Inventors: Hidetoshi SUGIYAMA, Shigeki MATSUBARA, Toshinari SAKURAI, Takayuki OBARA, Ryosuke KAWACHI
  • Patent number: 8765474
    Abstract: An automatic analyzer which assures uniformity in mixing effects regardless of sample quantity and test item and thus produces analysis results with high repeatability. The automatic analyzer includes a device for adding a conditioning liquid into a reaction chamber so that the quantity of liquid in the reaction chamber becomes a predetermined quantity prior to being mixed. The conditioning liquid may be a diluent or physiological saline as used for dilution of a sample or any other special liquid that adjusts the properties such as viscosity, surface tension, etc. of liquid to be mixed.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: July 1, 2014
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Katsuhiro Kambara, Shigenori Watari, Hidetoshi Sugiyama
  • Patent number: 8754632
    Abstract: An integrated circuit in which a power terminal, a ground terminal, an input terminal and an internal circuit are formed, has a unidirectional circuit of a direction from the input terminal to the power terminal, the unidirectional circuit being provided between the input terminal and the power terminal; and a power state determination circuit which detects whether the power terminal is connected to an external power source or not to output a power open detection signal. And the unidirectional circuit includes a first transistor in which a voltage of the power terminal is applied to a gate, and a second transistor connected to the first transistor in series, and a voltage of the external power source is input to the input terminal.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: June 17, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hidetoshi Sugiyama, Takayuki Nagasawa, Hideaki Suzuki
  • Patent number: 8409507
    Abstract: An automatic analyzer includes a status table storing the status of each analysis module and reagent information identifying each reagent, the supply of which is exhausted, and allowing tracking of the status of each analysis module, etc. The automatic analyzer determines, based on the status table, whether and how it can continue current analysis, and stores the determination results in its instruction information table. The instruction information table stores analysis-unit or -module operating information and information to be supplied to the user or operator. The analysis-unit operating information includes instructions for the analysis modules to initiate an analysis in a normal manner, finish an analysis in a normal manner, omit a pre-analysis operation, omit a post-analysis operation, or stop sampling, etc. Further, the reagent information and the analysis module status are updated each time a reagent container is replaced by the operator.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: April 2, 2013
    Assignees: Hitachi High-Technologies Corporation, Roche Diagnostics Operations, Inc.
    Inventors: Hirokazu Iwamatsu, Kazuhiro Nakamura, Satoshi Shibuya, Yasunao Awata, Hidetoshi Sugiyama, Werner Doppen, Dietmar Kappelhoff
  • Publication number: 20120074926
    Abstract: An integrated circuit in which a power terminal, a ground terminal, an input terminal and an internal circuit are formed, has a unidirectional circuit of a direction from the input terminal to the power terminal, the unidirectional circuit being provided between the input terminal and the power terminal; and a power state determination circuit which detects whether the power terminal is connected to an external power source or not to output a power open detection signal. And the unidirectional circuit includes a first transistor in which a voltage of the power terminal is applied to a gate, and a second transistor connected to the first transistor in series, and a voltage of the external power source is input to the input terminal.
    Type: Application
    Filed: June 14, 2011
    Publication date: March 29, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hidetoshi Sugiyama, Takayuki Nagasawa, Hideaki Suzuki
  • Patent number: 7750437
    Abstract: A semiconductor device has a rectifier circuit and integrated circuit on a semiconductor substrate of a first conduction type, and has a first well region in the substrate, a second well region in first well region, and a diode region formed in second well region and constituting a diode with second well region. The rectifier circuit is formed by the diodes. An input power supply terminal, changing between positive and negative potentials, is connected to second and first well regions of a first diode and to diode region of a second diode. A current supply terminal is provided in the vicinity of first well region of first diode, and is connected to the substrate and a prescribed power supply, so as to supply a current to the PN junction between the first well region and the semiconductor substrate when the input power supply terminal is at negative potential.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: July 6, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hideaki Suzuki, Hidetoshi Sugiyama
  • Patent number: 7603248
    Abstract: A testing circuit for a semiconductor device having a test mode in which the information about built-in memory cannot be read after conducting a test on a semiconductor device, and cutting a pad formed in a scribe area is provided. The scribe PAD and the scribe ROM are formed in the cutting area of a wafer. Upon power-up of a chip a, the power-on reset circuit transmits a reset signal to the mode register. After setting the initial resister value to “00”, a mode switch signal is input from the mode switch terminal, the scribe ROM is activated, and the test mode is set. In this process, a Manchester coded signal is provided from the scribe PAD, decoded by a clock of dividing frequency provided from the clock dividing circuit, the value of the register in the test mode in the mode register is set, and external reset is asserted or negated.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: October 13, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Hidetoshi Sugiyama, Masao Nakajima, Haruyuki Mouri, Hideaki Suzuki
  • Publication number: 20080240989
    Abstract: An automatic analyzer of the present invention includes a status table storing the status of each analysis module and reagent information identifying each reagent, the supply of which is exhausted, and allowing tracking of the status of each analysis module, etc. The automatic analyzer determines, based on the status table, whether and how it can continue current analysis, and stores the determination results in its instruction information table. The instruction information table stores analysis-unit or -module operating information and information to be supplied to the user or operator. The analysis-unit operating information includes instructions for the analysis modules to initiate an analysis in a normal manner, finish an analysis in a normal manner, omit a pre-analysis operation, omit a post-analysis operation, or stop sampling, etc. Further, the reagent information and the analysis module status are updated each time a reagent container is replaced by the operator.
    Type: Application
    Filed: March 27, 2008
    Publication date: October 2, 2008
    Inventors: Hirokazu IWAMATSU, Kazuhiro NAKAMURA, Satoshi SHIBUYA, Yasunao AWATA, Hidetoshi SUGIYAMA
  • Publication number: 20080213903
    Abstract: An automatic analyzer which assures uniformity in mixing effects regardless of sample quantity and test item and thus produces analysis results with high repeatability. The analyzer includes a device for adding a conditioning liquid into a reaction chamber so that the quantity of liquid in the reaction chamber becomes a predetermined quantity at latest just before mixing. The conditioning liquid may be a diluent or physiological saline as used for dilution of a sample or any other special liquid that adjusts the properties such as viscosity, surface tension, etc. of liquid to be mixed.
    Type: Application
    Filed: February 15, 2008
    Publication date: September 4, 2008
    Inventors: Katsuhiro KAMBARA, Shigenori WATARI, Hidetoshi SUGIYAMA
  • Patent number: 7360984
    Abstract: An automatic analyzer, comprising disposable parts such as large quantities of nozzle tips and reaction containers for use in sample analysis inspection, wherein the part rack (12) holding unused parts is raised from a lowest position to a rack separation station (A) by a lift for supply (14) and separated so that only the uppermost stacked part rack can remain on the rack separation station, the separated part rack is moved to a part take-out station (B) where parts on the part rack are taken out one by one from a movable holding part (59), and, by opening the floor part of the part take-out station (B) after part consumption, the used part rack is allowed to fall down and recovered on the lift (84) of a recovery lifter (15), whereby the supply of an unused part rack on which unused parts are loaded and the recovery of a used part rack can be performed with a compact system configuration.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: April 22, 2008
    Assignee: Roche Diagnostics Corp.
    Inventors: Hidetoshi Sugiyama, Katsuaki Takahashi, Hideyuki Yanami, Stephan Sattler
  • Publication number: 20070203662
    Abstract: A testing circuit for a semiconductor device having a test mode in which the information about built-in memory cannot be read after conducting a test on a semiconductor device, and cutting a pad formed in a scribe area is provided. The scribe PAD and the scribe ROM are formed in the cutting area of a wafer. Upon power-up of a chip a, the power-on reset circuit transmits a reset signal to the mode register. After setting the initial resister value to “00”, a mode switch signal is input from the mode switch terminal, the scribe ROM is activated, and the test mode is set. In this process, a Manchester coded signal is provided from the scribe PAD, decoded by a clock of dividing frequency provided from the clock dividing circuit, the value of the register in the test mode in the mode register is set, and external reset is asserted or negated.
    Type: Application
    Filed: June 26, 2006
    Publication date: August 30, 2007
    Inventors: Hidetoshi Sugiyama, Masao Nakajima, Haruyuki Mouri, Hideaki Suzuki
  • Publication number: 20060273403
    Abstract: A semiconductor device has a rectifier circuit and integrated circuit on a semiconductor substrate of a first conduction type, and has a first well region in the substrate, a second well region in first well region, and a diode region formed in second well region and constituting a diode with second well region. The rectifier circuit is formed by the diodes. An input power supply terminal, changing between positive and negative potentials, is connected to second and first well regions of a first diode and to diode region of a second diode. A current supply terminal is provided in the vicinity of first well region of first diode, and is connected to the substrate and a prescribed power supply, so as to supply a current to the PN junction between the first well region and the semiconductor substrate when the input power supply terminal is at negative potential.
    Type: Application
    Filed: September 19, 2005
    Publication date: December 7, 2006
    Inventors: Hideaki Suzuki, Hidetoshi Sugiyama
  • Patent number: 4303653
    Abstract: Organic phosphoric acid ester derivatives represented by the formula (I): ##STR1## wherein R and R', which may be the same or different, each represents an alkyl group, and A represents a group of atoms necessary to complete together with the two carbon atoms to which they are attached, a 6-membered heterocyclic group containing an oxygen atom as a heteroatom; a process for preparing the same and insecticidal, miticidal or nematocidal compositions containing the same as an active ingredient are disclosed; the compositions exhibit a high ability to control insect pests, mites, nematodes and unhygienic insects harmful to agricultural and horticultural crops.
    Type: Grant
    Filed: June 27, 1981
    Date of Patent: December 1, 1981
    Assignee: Kumiai Chemical Industry Co., Ltd.
    Inventors: Isao Chiyomaru, Hidetoshi Sugiyama, Koyata Niita, Kunihiko Fujimori, Tadayoshi Hirano, Osamu Tada