Abstract: In a method of manufacturing a semiconductor device, a first chip region and a second chip region are provided on a silicon wafer. A first resist pattern for the semiconductor device is to be formed in the first chip region, and the second chip region includes a plurality of characteristic evaluation regions for the semiconductor device, and a second resist pattern is to be formed in each of the plurality of characteristic evaluation regions for the semiconductor device. A data rate of the second chip region is determined based on a data rate of the first chip region. The data rate of the second chip region is determined such that a ratio of the data rate of the first chip region to the data rate of the second chip region is in a range of ¼ to 4.

Abstract: A method for making a semiconductor device having an inter-layer insulating film formed on a semiconductor substrate and contact plugs contacting with the surface of the semiconductor substrate includes forming, in an inter-layer insulating film formed on a semiconductor substrate, holes by anisotropic etching so that the surface of the semiconductor substrate is exposed, forming a CVD insulating film on the surface of the resulting wafer including the inner surface of each hole, heating in an oxygen-containing atmosphere to form a thermal oxide film at the surface portion of the semiconductor substrate at the bottom of each hole, etching back the CVD insulating film of the bottom of each hole while simultaneously removing the thermal oxide film formed in the thermal oxidation to expose the surface of the semiconductor substrate, and filling each hole with a conductive material to form each contact plug.

Abstract: In a method of manufacturing a semiconductor device, a first chip region and a second chip region are provided on a silicon wafer. A first resist pattern for the semiconductor device is to be formed in the first chip region, and the second chip region includes a plurality of characteristic evaluation regions for the semiconductor device, and a second resist pattern is to be formed in each of the plurality of characteristic evaluation regions for the semiconductor device. A data rate of the second chip region is determined based on a data rate of the first chip region. The data rate of the second chip region is determined such that a ratio of the data rate of the first chip region to the data rate of the second chip region is in a range of 1/4 to 4.

Abstract: A semiconductor device in which at least one lower electrode is formed on an insulating film formed on a semiconductor substrate, and a capacitive insulating film and an upper electrode are formed on a surface of said lower electrode, thereby forming a capacitive element, wherein said lower electrode has side walls each formed integrally on a side surface thereof and consisting of a conductive film whose lower end portion extends from a bottom surface of said lower electrode to a semiconductor substrate side.