Patents by Inventor Hidetsugu Irie

Hidetsugu Irie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240127692
    Abstract: An apparatus includes first and second chips. The first chip includes a first transmission control portion to generate a transmission signal, and a first transmitting coil connected to the first transmission control portion to transmit the transmission signal. The second chip includes a second receiving coil capable of receiving the transmission signal by being inductively coupled with the first transmitting coil, and a second detection portion to detect a voltage or current applied to the second receiving coil. The first and second chips are in close proximity to enable wireless communication through inductive coupling. The second detection portion is configured to detect, when a change in voltage or current occurring in the second receiving coil satisfies a predetermined condition, a change in relative position between the first chip and the second chip, or vibration applied to the first and second chips, pressure change, temperature change, or electromagnetic wave.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Inventors: Hidetsugu IRIE, Junichiro KADOMOTO, Hidenori TSUJI, Junta MIYAMOTO
  • Patent number: 11762640
    Abstract: An information conversion device has one of: a replication necessity analysis unit for specifying where an instruction referred by phi functions is present in one basic block and inserting a transfer instruction therein; an intra-loop constant analysis unit for specifying a closed path in which a phi function reference is circulated and inserting the transfer instruction therein; an inter-instruction dependency analysis unit for specifying where data dependency is present between instructions as a reference destination of the phi functions and inserting the transfer instruction therein; a same instruction reference analysis unit for specifying where the phi functions referring to a result of a same instruction before branching are present and inserting the transfer instruction therein; and a spill out validity analysis unit for storing a value present in a loop processing, loading the value after the loop processing ends, and deleting the transfer instruction.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: September 19, 2023
    Inventors: Hidetsugu Irie, Shuichi Sakai, Toru Koizumi, Satoshi Nakae, Akifumi Fukuda
  • Publication number: 20220415569
    Abstract: An information processing device is provided that can more flexibly adapt to changes in shape and mounting configuration. The information processing device has a plurality of chips that are integrated in the horizontal direction. A transmission coil and reception coil pair is formed in each of the plurality of chips, and each of the plurality of chips uses horizontal inductive coupling to achieve wireless connection between the chips.
    Type: Application
    Filed: November 20, 2020
    Publication date: December 29, 2022
    Inventors: Hidetsugu IRIE, Junichiro KADOMOTO, Shuichi SAKAI
  • Publication number: 20220236970
    Abstract: A program causes a computer to serve as an information conversion device that is equipped with at least one of (A)-(E): (A) a replication necessity analysis processor specifying a location where an instruction referred to from phi functions present in one basic block is present and inserting an inter-register transfer instruction therein; (B) an intra-loop constant analysis processor specifying a closed path in which the references of the phi functions are circulated and inserting the inter-register transfer instruction therein; (C) an inter-instruction dependency analysis processor specifying a location where data dependency is present between instructions, which are reference destinations of the phi functions, and inserting the inter-register transfer instruction thereat; (D) an identical instruction reference analysis processor specifying, in a plurality of execution paths, a location where the phi functions referring to a result of the identical instruction before branching are present and inserting the i
    Type: Application
    Filed: May 21, 2020
    Publication date: July 28, 2022
    Inventors: Hidetsugu IRIE, Shuichi SAKAI, Toru KOIZUMI, Satoshi NAKAE, Akifumi FUKUDA
  • Patent number: 8413240
    Abstract: An example of a device comprises a storage which stores data which is input from outside and to which tracking information is added, a section which detects a first reading event of first data from the storage to which the tracking information is added, a section which detects, after the first reading event, a first writing event to part of character string data to the storage, a section which detects, after the first writing event, a second reading event of second data from the storage to which the tracking information is added, a section which detects, after the second reading event, a second writing event to part of the character string data to the storage, and a section which adds, when the first reading/writing event, second reading/writing event are detected, the tracking information to data to be written to the storage by the first and second writing event.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: April 2, 2013
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Satoshi Katsunuma, Masahiro Goshima, Hidetsugu Irie, Ryota Shioya, Shuichi Sakai
  • Publication number: 20100083379
    Abstract: An example of a device comprises a storage which stores data which is input from outside and to which tracking information is added, a section which detects a first reading event of first data from the storage to which the tracking information is added, a section which detects, after the first reading event, a first writing event to part of character string data to the storage, a section which detects, after the first writing event, a second reading event of second data from the storage to which the tracking information is added, a section which detects, after the second reading event, a second writing event to part of the character string data to the storage, and a section which adds, when the first reading/writing event, second reading/writing event are detected, the tracking information to data to be written to the storage by the first and second writing event.
    Type: Application
    Filed: March 26, 2009
    Publication date: April 1, 2010
    Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER
    Inventors: Satoshi Katsunuma, Masahiro Goshima, Hidetsugu Irie, Ryota Shioya, Shuichi Sakai