Patents by Inventor Hidetsuna Hashimoto

Hidetsuna Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5700720
    Abstract: According to the method of manufacturing a semiconductor device having a multilayer interconnection structure, lower wires are formed on a semiconductor substrate. Then, a first reflow SiO.sub.2 film having a reflow form is formed on the semiconductor substrate and the lower wires by reacting SiH.sub.4 gas with H.sub.2 O.sub.2 in a vacuum at 650 Pa or less within a range from -10 to 10.degree.C. After the first reflow SiO.sub.2 film is formed, heat treatment is performed at a predetermined high temperature on the semiconductor substrate on which the first reflow SiO.sub.2 film, and a second reflow SiO.sub.2 film having a reflow form is formed on the semiconductor substrate and the lower wires by reacting SiH.sub.4 gas with H.sub.2 O.sub.2 in a vacuum at 650 Pa or less within a range from -10 to 10.degree.C. The heat treatment step performed after the first reflow SiO.sub.2 film forming step and the second reflow SiO.sub.2 film forming step subsequent thereto are respectively performed at least once.
    Type: Grant
    Filed: December 20, 1995
    Date of Patent: December 23, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hidetsuna Hashimoto
  • Patent number: 4988609
    Abstract: In a patterning method according to this invention, a surface region of a resist layer is solution-retarded by a developer, and, then, the resist layer is patterned. Therefore, a desired shape of a side wall of the resist layer may be obtained by varying a solubility of the resist layer, with the result that a resist pattern with the side wall orthogonal to a surface of the substrate or the overhung side may be formed.
    Type: Grant
    Filed: June 13, 1988
    Date of Patent: January 29, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidetsuna Hashimoto, Tiharu Kato, Hitoshi Tsuji
  • Patent number: 4985374
    Abstract: A manufacturing method of a semiconductor device of the present invention comprises a first step of exposing a periphery of a first region of a photoresist layer coating an insulating layer formed on a semiconductor substrate and a periphery of a second region for positioning, and a second step of heating said photoresist layer in ammonia atmosphere and forming an alkali insoluble portion in the periphery of the first region and that of the second region, a third step of exposing a third region, which is smaller than the first region, and the second region and developing these regions, a fourth step of etching the third region and the second region to a predetermined depth, and a fifth step of repeating the third and fourth steps once or more in a region, which is smaller than the third region, and the second region.
    Type: Grant
    Filed: June 27, 1990
    Date of Patent: January 15, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Tsuji, Hiroshi Haraguchi, Osamu Hirata, Hidetsuna Hashimoto