Abstract: In a charge pump-based PLL circuit, charge pump output current variation may cause phase instability at an output of a VCO. The output current variation may be caused by low-frequency disturbances (e.g., tuning voltage (Vtune) drift with channel length modulation effect), disturbance in a gate bias voltage of a transistor, or a VDD transient. Such a low-frequency disturbance may occur during initial lock, which may affect phase settling time, or after lock, which may result in phase instability. A replica charge pump and a current filtering and compensation circuit may be implemented at the output of a main charge pump to provide error current compensation to suppress channel length modulation effect, improve phase stability, and reduce phase noise.

Abstract: A phase shifter circuit may include a multiple phase shifter cells (or cells) to selectively shift a phase of an input signal by a desired phase shift value. For example, each of the phase shifter cells may shift the phase of the input signal by a positive fractional phase shift value or a negative fractional phase shift value. The phase shifter cells may include circuitry to form an inductor-capacitor circuit to provide the negative fractional phase shift value and form a capacitor-inductor circuit to provide the positive fractional phase shift value. The phase shifter cells may receive control signals to form the inductor-capacitor circuit and the capacitor-inductor circuit. An electronic device may include multiple phase shifter circuits to adjust a phase of transmission signals and/or reception signals of phased array antennas.

Abstract: In a charge pump-based PLL circuit, charge pump output current variation may cause phase instability at an output of a VCO. The output current variation may be caused by low-frequency disturbances (e.g., tuning voltage (Vtune) drift with channel length modulation effect), disturbance in a gate bias voltage of a transistor, or a VDD transient. Such a low-frequency disturbance may occur during initial lock, which may affect phase settling time, or after lock, which may result in phase instability. A replica charge pump and a current filtering and compensation circuit may be implemented at the output of a main charge pump to provide error current compensation to suppress channel length modulation effect, improve phase stability, and reduce phase noise.

Abstract: In a charge pump-based PLL circuit, charge pump output current variation may cause phase instability at an output of a VCO. The output current variation may be caused by low-frequency disturbances (e.g., tuning voltage (Vtune) drift with channel length modulation effect), disturbance in a gate bias voltage of a transistor, or a VDD transient. Such a low-frequency disturbance may occur during initial lock, which may affect phase settling time, or after lock, which may result in phase instability. A replica charge pump and a current filtering and compensation circuit may be implemented at the output of a main charge pump to provide error current compensation to suppress channel length modulation effect, improve phase stability, and reduce phase noise.

Abstract: A radio frequency switch having an N number of switch cells coupled in series is disclosed. Each of the switch cells includes a field-effect transistor (FET), wherein a source of switch cell 1 is coupled to a first port, a drain of switch cell N is coupled to a second port, and a drain of switch cell X is coupled to a source of switch cell X+1 for switch cell 1 through switch cell N. A first diode stack has a first anode coupled to the body of switch cell X and a first cathode coupled to a drain of switch cell X+1 for switch cell 1 through switch cell N?1, and a second diode stack has a second anode coupled to the body of switch cell X and a second cathode coupled to the source of switch cell X?1 for switch cell 2 through switch cell N.

Abstract: A radio frequency switch having an N number of switch cells coupled in series is disclosed. Each of the switch cells includes a field-effect transistor (FET), wherein a source of switch cell 1 is coupled to a first port, a drain of switch cell N is coupled to a second port, and a drain of switch cell X is coupled to a source of switch cell X+1 for switch cell 1 through switch cell N. A first diode stack has a first anode coupled to the body of switch cell X and a first cathode coupled to a drain of switch cell X+1 for switch cell 1 through switch cell N?1, and a second diode stack has a second anode coupled to the body of switch cell X and a second cathode coupled to the source of switch cell X?1 for switch cell 2 through switch cell N.

Abstract: A radio frequency switch having an N number of switch cells coupled in series is disclosed. Each of the switch cells includes a field-effect transistor (FET), wherein a source of switch cell 1 is coupled to a first port, a drain of switch cell N is coupled to a second port, and a drain of switch cell X is coupled to a source of switch cell X+1 for switch cell 1 through switch cell N. A first diode stack has a first anode coupled to the body of switch cell X and a first cathode coupled to a drain of switch cell X+1 for switch cell 1 through switch cell N?1, and a second diode stack has a second anode coupled to the body of switch cell X and a second cathode coupled to the source of switch cell X?1 for switch cell 2 through switch cell N.

Abstract: A power amplifier system is disclosed. The power amplifier system includes a power amplifier having a first signal input and a first signal output and a main bias circuitry configured to provide a first portion of a first bias signal to the power amplifier through a first bias output coupled to the first signal input. Further included is peak bias circuitry that is configured to provide a second portion of the first bias signal to the power amplifier through a second bias output coupled to the first signal input, wherein the first portion of the first bias signal is greater than the second portion of the first bias signal over a first input power range and the second portion of the first bias signal is greater than the first portion of the first bias signal over a second input power range that is greater than the first input power range.

Abstract: A transistor-based radio frequency (RF) switch that provides symmetric RF impedance is disclosed. The transistor-based RF switch includes an N number of main field-effect transistors (FETs) stacked in series between a first end node and a second end node. A first end-network is coupled between the first end node and a proximal gate node. The first end-network provides a first variable impedance that equalizes a drain-to-source voltage of the first main FET to within a predetermined percentage of a drain-to-source voltage of a second main FET of the N number of main FETs. A second end-network is coupled between the second end node and the distal gate node, wherein the second end-network provides a second variable impedance to equalize the drain-to-source voltage of an Nth main FET to within the predetermined percentage of the drain-to-source voltage of an N?1 main FET of the N number of main FETs.

Abstract: A power amplifier system is disclosed. The power amplifier system includes a power amplifier having a first signal input and a first signal output and a main bias circuitry configured to provide a first portion of a first bias signal to the power amplifier through a first bias output coupled to the first signal input. Further included is peak bias circuitry that is configured to provide a second portion of the first bias signal to the power amplifier through a second bias output coupled to the first signal input, wherein the first portion of the first bias signal is greater than the second portion of the first bias signal over a first input power range and the second portion of the first bias signal is greater than the first portion of the first bias signal over a second input power range that is greater than the first input power range.

Abstract: Improved Radio Frequency (RF) switches are provided herein. According to one aspect, an RF switch comprises one or more stages. In one embodiment, each stage comprises a signal input terminal, a signal output terminal, a control input terminal, and a switching device having a first terminal connected to the signal input terminal, a second terminal connected to the signal output terminal, and a third terminal for controlling the on/off state of the switching device. Each stage includes a first resistor connected in series between the control input terminal and the third terminal, a first bypass switch for electrically bypassing the first resistor, and a second resistor connected in series between the signal input terminal and the signal output terminal. The first resistors form a first bias network, the second resistors form a second bias network, and the switching devices are connected in series.

Abstract: A transistor-based radio frequency (RF) switch that provides symmetric RF impedance is disclosed. The transistor-based RF switch includes an N number of main field-effect transistors (FETs) stacked in series between a first end node and a second end node. A first end-network is coupled between the first end node and a proximal gate node. The first end-network provides a first variable impedance that equalizes a drain-to-source voltage of the first main FET to within a predetermined percentage of a drain-to-source voltage of a second main FET of the N number of main FETs. A second end-network is coupled between the second end node and the distal gate node, wherein the second end-network provides a second variable impedance to equalize the drain-to-source voltage of an Nth main FET to within the predetermined percentage of the drain-to-source voltage of an N?1 main FET of the N number of main FETs.

Abstract: Disclosed is a transistor-based switch having an N number of main field-effect transistors (FETs) stacked in series such that a first terminal of a first main FET of the N number of main FETs is coupled to a first end node and a second terminal of an Nth main FET of the N number of main FETs is coupled to a second end node, wherein N is a finite number greater than five. The transistor-based switch further includes a gate bias network having a plurality of gate resistors, wherein individual ones of the plurality of gate resistors are coupled to gate terminals of the N number of main FETs. A common gate resistor is coupled between a gate control input and a gate control node of the plurality of gate resistors, and a capacitor is coupled between the gate control node and a switch path node of the main FETs.

Abstract: A Radio Frequency (RF) switch having two or more stages coupled in series is disclosed. A first Field-Effect Transistor (FET) with a first control terminal is coupled across a gate resistor to shunt the gate resistor when the first FET is on. An RF switching device is configured to pass an RF signal between a signal input and a signal output when the RF switching device is on. A second FET having a second control terminal coupled to an acceleration output is configured to shunt the RF switching device when the second FET is on. A third FET is coupled between the first control terminal and the signal input for controlling charge on a gate of the first FET. A third control terminal of the third FET is coupled to an acceleration input for controlling an on/off state of the third FET.

Abstract: Disclosed is a transistor-based switch having an N number of main field-effect transistors (FETs) stacked in series such that a first terminal of a first main FET of the N number of main FETs is coupled to a first end node and a second terminal of an Nth main FET of the N number of main FETs is coupled to a second end node, wherein N is a finite number greater than five. The transistor-based switch further includes a gate bias network having a plurality of gate resistors, wherein individual ones of the plurality of gate resistors are coupled to gate terminals of the N number of main FETs. A common gate resistor is coupled between a gate control input and a gate control node of the plurality of gate resistors, and a capacitor is coupled between the gate control node and a switch path node of the main FETs.

Abstract: A Radio Frequency (RF) switch having two or more stages coupled in series is disclosed. A first Field-Effect Transistor (FET) with a first control terminal is coupled across a gate resistor to shunt the gate resistor when the first FET is on. An RF switching device is configured to pass an RF signal between a signal input and a signal output when the RF switching device is on. A second FET having a second control terminal coupled to an acceleration output is configured to shunt the RF switching device when the second FET is on. A third FET is coupled between the first control terminal and the signal input for controlling charge on a gate of the first FET. A third control terminal of the third FET is coupled to an acceleration input for controlling an on/off state of the third FET.

Abstract: Improved Radio Frequency (RF) switches are provided herein. According to one aspect, an RF switch comprises one or more stages. In one embodiment, each stage comprises a signal input terminal, a signal output terminal, a control input terminal, and a switching device having a first terminal connected to the signal input terminal, a second terminal connected to the signal output terminal, and a third terminal for controlling the on/off state of the switching device. Each stage includes a first resistor connected in series between the control input terminal and the third terminal, a first bypass switch for electrically bypassing the first resistor, and a second resistor connected in series between the signal input terminal and the signal output terminal. The first resistors form a first bias network, the second resistors form a second bias network, and the switching devices are connected in series.

Abstract: A method and apparatus improves the accuracy of temperature measurements by sampling measurements from a remote sensor, where currents of different current densities are applied to the remote sensor in a time-interleaved fashion. The remote sensor includes at least one PN junction that produces a voltage corresponding to the applied current at each instance of time, and related to the temperature of the remote sensor. By applying time-interleaved current densities to the remote sensor, adverse effects from temperature variations during the measurement are minimized. Sequences of current biases having differing current densities in a forward order are applied to the remote sensor, followed by the same sequence being applied to the remote sensor in a reverse order. Similarly, a random or pseudo-random sequence may be employed in a forward and reverse order. The application of forward and reverse sequences is utilized to minimize errors in the temperature measurement.