Patents by Inventor Hideyasu Murooka

Hideyasu Murooka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5480048
    Abstract: A multilayer wiring board fabricating method and a multilayer wiring board fabricated with use of the method that a solvent-free fluid polymer precursor is put on a wiring layer of a base substrate, and space among the wirings is exhausted and is filled with the precursor, and the precursor is hardened under a hydrostatic pressure and then the next wiring layer is formed before the above process is repeated one or more times. The multilayer wiring board fabricating method is excellent in the mass productivity and low cost and in that the wiring can be made highly dense with the substrate having vertical via conductors for connection among the conductor layers.
    Type: Grant
    Filed: August 30, 1993
    Date of Patent: January 2, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Naoya Kitamura, Hisashi Sugiyama, Yoshihide Yamaguchi, Masayuki Kyoui, Hideyasu Murooka, Ryoji Iwamura, Makio Watanabe
  • Patent number: 5388328
    Abstract: A process for the fabrication of an interconnected multilayer board involves the steps of forming a metallic under-conductive layer on a base substrate, forming a windowed resist layer on the metallic under-conductive layer, filling windows of the resist layer with a conductor by plating thereby forming a conductor layer, forming another windowed resist layer on the conductor layer and filling windows of this resist layer with a conductor by plating, thereby forming a via-hole layer and to provide a two-level structure of the conductor layer and the via-hole layer. Thereafter, the resist layers and portions of the metallic under-conductor layer other than those in contact with a lower face of the conductor constituting the conductor layer are dissolved to form a two-level skeleton structure of conductor lines and spaces within the skeleton structure are filled with a varnish in a solventless form and the varnish is cured.
    Type: Grant
    Filed: January 28, 1994
    Date of Patent: February 14, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Hitoshi Yokono, Hideo Arima, Takashi Inoue, Naoya Kitamura, Haruhiko Matsuyama, Hitoshi Oka, Fumio Kataoka, Fusaji Shoji, Hideyasu Murooka, Masayuki Kyooi
  • Patent number: 5300735
    Abstract: Described herein are interconnected mutilayer boards and their fabrication processes. Multilayer conductor lines of a skeleton structure are formed by conducting multilayer metallization while including all resist layers and metallic under-conductive layers and then removing the resist layers and metallic under-conductive layers at once. Spaces between the multilayer conductor lines of the skeleton structure are then filled with a solventless varnish so that insulating layers are formed. Modules making use of such interconnected multilayer boards and computers having such modules are also described.
    Type: Grant
    Filed: March 22, 1993
    Date of Patent: April 5, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Hitoshi Yokono, Hideo Arima, Takashi Inoue, Naoya Kitamura, Haruhiko Matsuyama, Hitoshi Oka, Fumio Kataoka, Fusaji Shoji, Hideyasu Murooka, Masayuki Kyooi
  • Patent number: 5182121
    Abstract: A hot press including a displaceable sleeve for surrounding materials of a multi-layer substrate under a reduced pressure condition, a gas pressurizing condition and a heating condition with thermal plates. Upper and lower sealing units seal an interior of the sleeve, with a mechanism lowering and raising the sleeve. A pilot check mechanism prevents a lower bolster from raising/lowering upon the reduced pressure condition and the gas pressure condition, and a retainer maintains the lowered or raised condition of the sleeve. The multi-layer substrate is formed under the reduced pressure condition and the gas pressure condition. Accordingly, the atmosphere and moisture between the materials of the multi-layer substrate and volatile composition are removed. Additionally, a void generated during the heat and pressure process by the heating plates is eliminated from the multi-layer substrate.
    Type: Grant
    Filed: October 9, 1990
    Date of Patent: January 26, 1993
    Assignees: Hitachi, Ltd., Hitachi Techno Engineering Co., Ltd.
    Inventors: Akimi Miyashita, Mutsumasa Fujii, Minoru Kubosawa, Keiichiro Torii, Nobuaki Ooki, Kiyonori Kogawa, Masami Kawaguchi, Hideyasu Murooka, Masayuki Kyooi
  • Patent number: 4908087
    Abstract: A method and an apparatus of forming a multilayer printed circuit board which can positively remove voids in the prepregs in the printed board and enhance the reliability of the produced printed circuit board and is superior in economy, wherein a laminated assembly of a plurality of printed circuit board components and a plurality of prepregs alternately laminated on each other is sandwiched between upper and lower jig plates, and the laminated assembly sandwiched between the jig plates is clamped between heating plates of a bonding press to heat the assembly to a predetermined temperature, and, thereafter, a pressure is applied to the upper and lower jig plates so as to urge them against each other for bonding the printed circuit board component and the prepregs.
    Type: Grant
    Filed: March 31, 1989
    Date of Patent: March 13, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Hideyasu Murooka, Masayuki Kyooi, Osamu Yamada, Noriaki Ujiie
  • Patent number: 4557792
    Abstract: A hot press capable of minimizing a displacement of one substrate from another in multilayer printed circuit boards each constituted by a plurality of substrates having wiring pattern groups printed thereon which are pressed together by applying pressure into a multilayer printed circuit board. The end is attained by minimizing a variation in thickness from a central portion of the board to a peripheral portion thereof. The hot press includes plate thickness adjusting devices each interposed between each bolster and each heat insulating member to compress and deform the heat insulating members beforehand.
    Type: Grant
    Filed: April 16, 1984
    Date of Patent: December 10, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Osamu Yamada, Hideyasu Murooka, Kaoru Ono, Akimi Miyashita