Abstract: A power supply control circuit includes a mode controlling unit which, in accordance with an output voltage of an amplifying section, performs a mode up for switching a current power supply voltage of the amplifying section to a higher power supply voltage being higher than the current power supply voltage, and which, in a case where a magnitude of the output voltage of the amplifying section is smaller than a threshold voltage for a predetermined time period or longer, performs a mode down for switching the power supply voltage of the amplifying section to a lower power supply voltage being lower than the current power supply voltage, and a threshold setting unit which sets the threshold voltage based on the output voltage of the amplifying section at a timing when the mode up is performed.

Abstract: A power supply control circuit includes a mode controlling unit which, in accordance with an output voltage of an amplifying section, performs a mode up for switching a current power supply voltage of the amplifying section to a higher power supply voltage being higher than the current power supply voltage, and which, in a case where a magnitude of the output voltage of the amplifying section is smaller than a threshold voltage for a predetermined time period or longer, performs a mode down for switching the power supply voltage of the amplifying section to a lower power supply voltage being lower than the current power supply voltage, and a threshold setting unit which sets the threshold voltage based on the output voltage of the amplifying section at a timing when the mode up is performed.

Abstract: A chopper comparator has inverters in input and output stages including NMOS transistors to control connection and disconnection of an inverter circuit of each inverter. During a non-operation period of the chopper comparator, parts of the inverters are disconnected form the ground based on a signal supplied to gates of the NMOS transistors.

Abstract: A chopper comparator has inverters (1,2) in input and output stages including NMOS transistors (M3,M6) to control the connection and disconnection of an inverter circuit forming each inverter (1,2). During a non-operation period of the chopper comparator, circuits formed in the inverters (1,2) are disconnected form the ground based on a PS signal to be supplied to gates of the NMOS transistors (M3,M6).

Abstract: In a semiconductor substrate, at least one diffusion region exists between resistors on an element isolation layer, and the resistors and the diffusion regions are arranged such that all distances between the respective resistors and the diffusion regions around the corresponding resistors are equal.

Abstract: A method of fabricating a semiconductor device includes burying Cu wiring with an insulating interlayer film and a first insulating film for preventing diffusion of copper on a planarized surface, including the Cu wiring, of which copper is the uppermost layer, and with a second insulating film having high moisture resistance. A photosensitive polyimide material is applied to the insulating film, exposed, and developed, thereby forming an etching mask. The etching mask is cured. Using the cured etching mask, the insulating films are etched to expose the Cu wiring as the uppermost layer.

Abstract: A semiconductor device, having a multi-layer interconnection structure, is provided which comprises a semiconductor substrate and a plurality of interlayer insulating films formed on the semiconductor substrate. A plurality of conductive leads are formed in the interlayer insulating films. In one of the interlayer insulating films having conductive lead or leads, at least one conductive plug is formed vertically to connect the conductive leads in different interlayer insulating films. Further, adjacent conductive leads may be formed in an adjacent interlayer insulating films are connected together to form a unified conductive lead.

Abstract: A method of fabricating a semiconductor device includes following four steps. (1) Cu wiring is buried in an insulating interlayer film, an insulating film for preventing diffusion of copper is deposited on a planarized surface including the Cu wiring as the uppermost layer, and another insulating film having high moisture resistance is deposited. (2) On the insulating film, a photosensitive polyimide material is applied, exposed, and developed, thereby forming an etching mask. (3) The etching mask is cured. (4) By using the cured etching mask, the insulating films are etched to expose the Cu wiring as the uppermost layer.

Abstract: At least one diffusion region exists between a plurality of resistors formed on an element isolation layer, and the plurality of resistors and the diffusion regions are arranged such that all distances between the respective resistors and the diffusion regions around the corresponding resistors are equal to each other.

Abstract: A semiconductor device, having a multi-layer interconnection structure, is provided which comprises a semiconductor substrate and a plurality of interlayer insulating films formed on the semiconductor substrate. A plurality of conductive leads are formed in the interlayer insulating films. In one of the interlayer insulting films having conductive lead or leads, at least one conductive plug is formed vertically to connect the conductive leads in different interlayer insulating films. Further, adjacent conductive leads may be formed in an adjacent interlayer insulating films are connected together to form a unified conductive lead.

Abstract: A method of fabricating a semiconductor device includes following four steps. (1) Cu wiring is buried in an insulating interlayer film, an insulating film for preventing diffusion of copper is deposited on a planarized surface including the Cu wiring as the uppermost layer, and another insulating film having high moisture resistance is deposited. (2) On the insulating film, a photosensitive polyimide material is applied, exposed, and developed, thereby forming an etching mask. (3) The etching mask is cured. (4) By using the cured etching mask, the insulating films are etched to expose the Cu wiring as the uppermost layer.

Abstract: A metal wire comprising a metal member and a barrier metal is formed within each of trenches formed in an insulating film placed on a semiconductor substrate. A first metal diffusion preventive film is formed on the insulating film so as to make contact with an upper portion of the barrier metal formed on the sides of the metal. Further, a second metal diffusion preventive film is formed on the first metal diffusion preventive film and the metal wire.

Abstract: A method of manufacturing a semiconductor device which prevents a short circuit between a gate electrode and a diffusion layer region if a contact hole is shifted from its proper position. A material having an etch selectivity to an interlayer insulation film is formed over the gate electrode to serve as a cover against the formation of a contact hole. A material is not formed over an interconnect line which is required to be exposed to a contact hole.