Abstract: An analog multiplexer comprises MOS FET circuits of (n+1) in number corresponding to analog input terminals of (n+1) in number, and circuits of (n+1) in number for applying a fixed electric potential to the MOS FET circuits, where n is a positive integer (in =1, 2, 3, . . . ). The MOS FET circuit includes first and second MOS FET pairs each including n and p-channel MOS FETs which are connected to face each other. In a selected state of an analog signal, a corresponding MOS FET circuit is turned on in the application of a selection signal to gate electrodes of the n-channel MOS FETs and an inverted signal of the selection signal to gate electrodes of the p-channel MOS FETs. In a non-selected state of an analog signal, corresponding MOS FET circuits are turned on, and the fixed electric potential is applied to a connecting point between the first and second MOS FET pairs in each non-selected MOS FET circuit.