Patents by Inventor Hideyo Okushi
Hideyo Okushi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10066317Abstract: A method for manufacturing a single crystal diamond in which vapor phase synthetic single crystal diamond is additionally deposited on a single crystal diamond seed substrate obtained by vapor phase synthesis, includes a step of measuring flatness of the seed substrate, a step of determining whether or not to flatten the seed substrate based on the measurement result of the flatness, and any one of the following two steps of a step of additionally depositing the vapor phase synthetic single crystal diamond after flattening the seed substrate for which the flattening is necessary based on the determination and a step of additionally depositing the vapor phase synthetic single crystal diamond without flattening the seed substrate for which the flattening is not necessary based on the determination.Type: GrantFiled: September 17, 2014Date of Patent: September 4, 2018Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, SHIN-ETSU CHEMICAL CO., LTD.Inventors: Hitoshi Noguchi, Daisuke Takeuchi, Satoshi Yamasaki, Masahiko Ogura, Hiromitsu Kato, Toshiharu Makino, Hideyo Okushi
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Patent number: 9136400Abstract: In this junction element 1, when a forward voltage is applied, a depletion layer is formed in a semiconductor layer 2, prohibiting electrons present in an electrode layer 4 to move into the semiconductor layer 2. For this reason, a majority of holes in a semiconductor layer 3 do not disappear by recombination with conduction electrons in the semiconductor layer 2, but reach the electrode layer 4 while diffusing into the semiconductor layer 2. Accordingly, the junction element 1 can serve as a good conductor for holes, while avoiding the influence of a resistance value, and allows a current to flow therethrough at a level equal to or more than that achieved by a semiconductor element formed of a Si or SiC semiconductor.Type: GrantFiled: February 27, 2009Date of Patent: September 15, 2015Assignees: NISSAN MOTOR CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Satoshi Tanimoto, Norihiko Kiritani, Toshiharu Makino, Masahiko Ogura, Norio Tokuda, Hiromitsu Kato, Hideyo Okushi, Satoshi Yamasaki
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Publication number: 20150075420Abstract: A method for manufacturing a single crystal diamond in which vapor phase synthetic single crystal diamond is additionally deposited on a single crystal diamond seed substrate obtained by vapor phase synthesis, includes a step of measuring flatness of the seed substrate, a step of determining whether or not to flatten the seed substrate based on the measurement result of the flatness, and any one of the following two steps of a step of additionally depositing the vapor phase synthetic single crystal diamond after flattening the seed substrate for which the flattening is necessary based on the determination and a step of additionally depositing the vapor phase synthetic single crystal diamond without flattening the seed substrate for which the flattening is not necessary based on the determination.Type: ApplicationFiled: September 17, 2014Publication date: March 19, 2015Inventors: Hitoshi NOGUCHI, Daisuke TAKEUCHI, Satoshi YAMASAKI, Masahiko OGURA, Hiromitsu KATO, Toshiharu MAKINO, Hideyo OKUSHI
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Patent number: 8624263Abstract: The present invention is contemplated for providing a diamond semiconductor device where an impurity-doped diamond semiconductor is buried in a selected area, and a method of manufacturing the same. That is, a diamond semiconductor device having an impurity-doped diamond area selectively buried in a recessed portion formed in a diamond substrate; and a method of manufacturing a diamond semiconductor device, including the steps of selectively forming an recessed portion on the {100}-facet diamond semiconductor substrate, wherein the bottom face of the recessed portion is surrounded by the {100} facet and the side face of the recessed portion is surrounded by the {110} facet, and forming an impurity-doped diamond area by epitaxially growing diamond in the <111> direction while doping with impurities and burying the recessed portion.Type: GrantFiled: March 6, 2009Date of Patent: January 7, 2014Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Hiromitsu Kato, Toshiharu Makino, Masahiko Ogura, Hideyo Okushi, Satoshi Yamasaki
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Publication number: 20110037076Abstract: The present invention is contemplated for providing a diamond semiconductor device where an impurity-doped diamond semiconductor is buried in a selected area, and a method of manufacturing the same. That is, a diamond semiconductor device having an impurity-doped diamond area selectively buried in a recessed portion formed in a diamond substrate; and a method of manufacturing a diamond semiconductor device, including the steps of selectively forming an recessed portion on the {100}-facet diamond semiconductor substrate, wherein the bottom face of the recessed portion is surrounded by the {100} facet and the side face of the recessed portion is surrounded by the {110} facet, and forming an impurity-doped diamond area by epitaxially growing diamond in the <111> direction while doping with impurities and burying the recessed portion.Type: ApplicationFiled: March 6, 2009Publication date: February 17, 2011Inventors: Hiromitsu Kato, Toshiharu Makino, Masahiko Ogura, Hideyo Okushi, Satoshi Yamasaki
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Publication number: 20110017991Abstract: In this junction element 1, when a forward voltage is applied, a depletion layer is formed in a semiconductor layer 2, prohibiting electrons present in an electrode layer 4 to move into the semiconductor layer 2. For this reason, a majority of holes in a semiconductor layer 3 do not disappear by recombination with conduction electrons in the semiconductor layer 2, but reach the electrode layer 4 while diffusing into the semiconductor layer 2. Accordingly, the junction element 1 can serve as a good conductor for holes, while avoiding the influence of a resistance value, and allows a current to flow therethrough at a level equal to or more than that achieved by a semiconductor element formed of a Si or SiC semiconductor.Type: ApplicationFiled: February 27, 2009Publication date: January 27, 2011Inventors: Satoshi Tanimoto, Norihiko Kiritani, Toshiharu Makino, Masahiko Ogura, Norio Tokuda, Hiromitsu Kato, Hideyo Okushi, Satoshi Yamasaki
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Patent number: 7535025Abstract: In silicon carbide semiconductor device and manufacturing method therefor, a metal electrode which is another than a gate electrode and which is contacted with a singlecrystalline silicon carbide substrate is treated with a predetermined heat process at a temperature which is lower than a thermal oxidization temperature by which a gate insulating film is formed and is sufficient to carry out a contact annealing between the singlecrystalline silicon carbide substrate and a metal after a whole surrounding of the gate insulating film is enclosed with the singlecrystalline silicon carbide substrate, a field insulating film, and the gate electrode. The present invention is applicable to a MOS capacitor, an n channel planar power MOSFET, and an n channel planar power IGBT.Type: GrantFiled: December 6, 2004Date of Patent: May 19, 2009Assignees: Nissan Motor Co., Ltd., National Institute of Advanced Industrial Science and TechnologyInventors: Satoshi Tanimoto, Hideyo Okushi
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Publication number: 20050093000Abstract: In silicon carbide semiconductor device and manufacturing method therefor, a metal electrode which is another than a gate electrode and which is contacted with a singlecrystalline silicon carbide substrate is treated with a predetermined heat process at a temperature which is lower than a thermal oxidization temperature by which a gate insulating film is formed and is sufficient to carry out a contact annealing between the singlecrystalline silicon carbide substrate and a metal after a whole surrounding of the gate insulating film is enclosed with the singlecrystalline silicon carbide substrate, a field insulating film, and the gate electrode. The present invention is applicable to a MOS capacitor, an n channel planar power MOSFET, and an n channel planar power IGBT.Type: ApplicationFiled: December 6, 2004Publication date: May 5, 2005Applicants: NISSAN MOTOR CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Satoshi Tanimoto, Hideyo Okushi
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Patent number: 6833562Abstract: In silicon carbide semiconductor device and manufacturing method therefor, a metal electrode which is another than a gate electrode and which is contacted with a singlecrystalline silicon carbide substrate is treated with a predetermined heat process at a temperature which is lower than a thermal oxidization temperature by which a gate insulating film is formed and is sufficient to carry out a contact annealing between the singlecrystalline silicon carbide substrate and a metal after a whole surrounding of the gate insulating film is enclosed with the singlecrystalline silicon carbide substrate, a field insulating film, and the gate electrode. The present invention is applicable to a MOS capacitor, an n channel planar power MOSFET, and an n channel planar power IGBT.Type: GrantFiled: December 2, 2002Date of Patent: December 21, 2004Assignees: Nissan Motor Co., Ltd., National Institute of Advanced Industrial Science and TechnologyInventors: Satoshi Tanimoto, Hideyo Okushi
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Patent number: 6815721Abstract: A diamond semiconductor has an exciton light-emission intensity characteristic that varies nonlinearly.Type: GrantFiled: March 8, 2004Date of Patent: November 9, 2004Assignee: Agency of Industrial Science & Technology, Ministry of International Trade & IndustryInventors: Hideyo Okushi, Hideyuki Watanabe, Daisuke Takeuchi, Koji Kajimura
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Publication number: 20040169178Abstract: A diamond semiconductor has an exciton light-emission intensity characteristic that varies nonlinearly.Type: ApplicationFiled: March 8, 2004Publication date: September 2, 2004Applicant: Agency of Ind Sci & Tech Min of Int'l Trade & IndInventors: Hideyo Okushi, Hideyuki Watanabe, Daisuke Takeuchi, Koji Kajimura
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Patent number: 6756086Abstract: A diamond semiconductor includes a high-quality thin diamond film layer with few crystal defects and few impurities, implanted with ions of dopant elements and controllable in conductivity determined by a kind and a concentration of the dopant elements. The diamond semiconductor is fabricated by a method including the step of implanting ions of dopant elements into a high-quality thin diamond film layer with few crystal defects and few impurities under conditions that can attain given distribution of concentrations of the dopant elements and with the high-quality thin diamond film layer kept to a temperature in accordance with the conditions so as not to be graphitized, to thereby enable the diamond semiconductor to have conductivity determined by a kind and a concentration of the dopant elements.Type: GrantFiled: March 6, 2002Date of Patent: June 29, 2004Assignees: Agency of Industrial Science and Technology, Ministry of International Trade and Industry, Japan Science and Technology CorporationInventors: Masataka Hasegawa, Masahiko Ogura, Daisuke Takeuchi, Hideyo Okushi, Naoto Kobayashi, Sadanori Yamanaka
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Patent number: 6727171Abstract: A diamond pn junction diode includes a p-type diamond thin-film layer formed on a substrate and an n-type diamond thin-film layer formed by forming a high-quality undoped diamond thin-film layer on the p-type diamond thin-film layer and ion-implanting an impurity into the high-quality undoped diamond thin-film layer, or alternatively includes an n-type diamond thin-film layer formed on a substrate and a p-type diamond thin-film layer formed by forming a high-quality undoped diamond thin-film layer on the n-type diamond thin-film layer and ion-implanting an impurity into the high-quality undoped diamond thin-film layer.Type: GrantFiled: February 20, 2003Date of Patent: April 27, 2004Inventors: Daisuke Takeuchi, Hideyuki Watanabe, Hideyo Okushi, Masataka Hasegawa, Masahiko Ogura, Naoto Kobayashi, Koji Kajimura, Sadanori Yamanaka
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Publication number: 20030155654Abstract: A diamond pn junction diode includes a p-type diamond thin-film layer formed on a substrate and an n-type diamond thin-film layer formed by forming a high-quality undoped diamond thin-film layer on the p-type diamond thin-film layer and ion-implanting an impurity into the high-quality undoped diamond thin-film layer, or alternatively includes an n-type diamond thin-film layer formed on a substrate and a p-type diamond thin-film layer formed by forming a high-quality undoped diamond thin-film layer on the n-type diamond thin-film layer and ion-implanting an impurity into the high-quality undoped diamond thin-film layer.Type: ApplicationFiled: February 20, 2003Publication date: August 21, 2003Applicant: Agy Indust'l Sci & Tech, Min Int'l Trade & IndstryInventors: Daisuke Takeuchi, Hideyuki Watanabe, Hideyo Okushi, Masataka Hasegawa, Masahiko Ogura, Naoto Kobayashi, Koji Kajimura, Sadanori Yamanaka
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Publication number: 20030107041Abstract: In silicon carbide semiconductor device and manufacturing method therefor, a metal electrode which is another than a gate electrode and which is contacted with a singlecrystalline silicon carbide substrate is treated with a predetermined heat process at a temperature which is lower than a thermal oxidization temperature by which a gate insulating film is formed and is sufficient to carry out a contact annealing between the singlecrystalline silicon carbide substrate and a metal after a whole surrounding of the gate insulating film is enclosed with the singlecrystalline silicon carbide substrate, a field insulating film, and the gate electrode. The present invention is applicable to a MOS capacitor, an n channel planar power MOSFET, and an n channel planar power IGBT.Type: ApplicationFiled: December 2, 2002Publication date: June 12, 2003Applicant: Nissan Motor Co., Ltd.Inventors: Satoshi Tanimoto, Hideyo Okushi
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Publication number: 20020127405Abstract: A diamond semiconductor includes a high-quality thin diamond film layer with few crystal defects and few impurities, implanted with ions of dopant elements and controllable in conductivity determined by a kind and a concentration of the dopant elements. The diamond semiconductor is fabricated by a method including the step of implanting ions of dopant elements into a high-quality thin diamond film layer with few crystal defects and few impurities under conditions that can attain given distribution of concentrations of the dopant elements and with the high-quality thin diamond film layer kept to a temperature in accordance with the conditions so as not to be graphitized, to thereby enable the diamond semiconductor to have conductivity determined by a kind and a concentration of the dopant elements.Type: ApplicationFiled: March 6, 2002Publication date: September 12, 2002Applicant: Agency of Industrial Science and TechnologyInventors: Masataka Hasegawa, Masahiko Ogura, Daisuke Takeuchi, Hideyo Okushi, Naoto Kobayashi, Sadanori Yamanaka
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Publication number: 20010025955Abstract: A diamond semiconductor has an exciton light-emission intensity characteristic that varies nonlinearly.Type: ApplicationFiled: December 8, 2000Publication date: October 4, 2001Applicant: AGENCY OF INDUSTRIAL SCIENCE & TECHNOLOGY, MINISTRY OF INTERNATIONAL TRADE & INDUSTRYInventors: Hideyo Okushi, Hideyuki Watanabe, Daisuke Takeuchi, Koji Kajimura
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Patent number: 6132816Abstract: A method for producing homoepitaxial diamond thin film is provided which includes a step of effecting plasma assisted CVD with the carbon source concentration of a mixed gas of a carbon source and hydrogen set to a first low level for depositing a high-quality homoepitaxial diamond thin film on a substrate at a low film forming rate and a step of thereafter effecting the plasma assisted CVD with said carbon source concentration set to a second level higher than the first level.Type: GrantFiled: October 21, 1998Date of Patent: October 17, 2000Assignee: Agency of Industrial Science & Technology, Ministry of International Trade and IndustryInventors: Daisuke Takeuchi, Hideyo Okushi, Koji Kajimura, Hideyuki Watanabe
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Patent number: 4532373Abstract: An amorphous photovoltaic energy conversion element for use in a solar cell is composed of a first layer formed of a p-type material, a second layer formed of an intrinsic amorphous semiconductor having a potential gradient formed therein and a third layer formed of a metal capable of coming into ohmic contact with the aforementioned intrinsic layer of amorphous semiconductor and exhibiting a lower work function than the work function of the intrinsic layer of amorphous semiconductor.Type: GrantFiled: March 14, 1984Date of Patent: July 30, 1985Assignee: Agency of Industrial Science & Technology, Ministry of International Trade and IndustryInventors: Hideharu Matsuura, Kazunobu Tanaka, Akihisa Matsuda, Hideyo Okushi, Hidetoshi Oheda, Satoshi Yamasaki, Nobuhiro Hata