Abstract: A data converting apparatus includes a video encode or decode operation unit which decodes a bit stream into a video signal; an IO buffer into which the bit stream transferred from an encoded-video recorder is stored; and a DMAC which controls a process of determining, in accordance with free space of the IO buffer and an OP buffer, either a first path going through a main memory or a second path bypassing the main memory as the transfer path, and having the bit stream, that is stored in the IO buffer, inputted into the video encode or decode operation unit via the determined transfer path.

Abstract: A cache memory device includes: a storage unit in which data and attribute information can be stored in association with each other; and a cache controller which (i) obtains, from CPU, a request signal requesting access to data and an indication signal indicating whether or not the requested data is a synchronization primitive, and when the indication signal indicates that the data requested by the request signal is the synchronization primitive, (ii) stores in association, into the storage unit, the requested data and synchronization primitive attribute information indicating that the requested data is a valid synchronization primitive. The cache controller prohibits purge of the data stored in the storage unit in association with the synchronization primitive attribute information.

Abstract: A data transfer apparatus according to the present invention has; a DMAC and another DMAC which transfer data by direct memory access among a plurality of buses; a command queue which holds, as a queue, commands for instructing the data transfer; a bus information obtainment unit which obtains the commands from the command queue; a grouping unit which groups the held commands, based on a source and a destination designated in each of the obtained commands; a schedule unit which decides an order of issuing the commands sequentially from a group having more command, as a priority; and a selector which selects a command to be issued according to the decided order.

Abstract: The decoding apparatus in the present invention includes a memory operable to hold encoded data representing one of a compressed sound and a compressed image, a memory read-out unit operable to sequentially read out the encoded data from said memory, a match determining circuit operable to determine whether or not data matching a specific bit sequence exists in the encoded data read out by said memory read-out unit, a deleting circuit operable to delete a part of the specific bit sequence from the encoded data read out from said memory, when said match determining circuit determines that the specific bit sequence exists, and a decoding circuit operable to decode the post-deletion encoded data.

Abstract: A data transfer apparatus according to the present invention has; a DMAC and another DMAC which transfer data by direct memory access among a plurality of buses; a command queue which holds, as a queue, commands for instructing the data transfer; a bus information obtainment unit which obtains the commands from the command queue; a grouping unit which groups the held commands, based on a source and a destination designated in each of the obtained commands; a schedule unit which decides an order of issuing the commands sequentially from a group having more command, as a priority; and a selector which selects a command to be issued according to the decided order.

Abstract: A video codec is composed of: a video encode/decode operation unit which decodes a bitstream into a video signal; an IO buffer into which the bitstream transferred from an encoded-video recorder is stored; and a DMAC which controls a process of determining, in accordance with free space of the IO buffer and an OP buffer, either a first path going through a main memory or a second path bypassing the main memory 11 as the transfer path, and having the bitstream, that is stored in the IO buffer, inputted into the video encode/decode operation unit via the determined transfer path.

Abstract: The decoding apparatus in the present invention includes a memory operable to hold encoded data representing one of a compressed sound and a compressed image, a memory read-out unit operable to sequentially read out the encoded data from said memory, a match determining circuit operable to determine whether or not data matching a specific bit sequence exists in the encoded data read out by said memory read-out unit, a deleting circuit operable to delete a part of the specific bit sequence from the encoded data read out from said memory, when said match determining circuit determines that the specific bit sequence exists, and a decoding circuit operable to decode the post-deletion encoded data.

Abstract: A FIFO memory device for inputting/outputting data having variable lengths of the present invention, includes: a first holding portion for holding data having a maximum data length MAX of input data to be input to the FIFO memory device; a second holding portion for holding residue data having a data length shorter than the maximum data length; and an input selecting portion for selectively inputting the input data to the first holding portion and the second holding portion in accordance with a data length IBP of the residue data and a data length WB of the input data.

Abstract: A data processing apparatus and method for floating point data used in a central processing unit for a digital computer effects the four fundamental arithmetic computations of floating point data and the rounding and normalizing computations. In the case of the floating point addition or subtraction, the mantissa portion of the two floating point data and a generated round addition value are summed using a single adder and, in the case of multiplication, a sum output and a carry output of a multiplying unit and a generated round addition value are added using a single adder, so as to correct the least significant bit of the output of the adder or the round addition value is again added. Since the need of effecting readdition for rounding is small, the average processing step numbers becomes small in comparison with the conventional techniques, and, since the mantissa operation and rounding are effected using the same adder at the same time, less hardware is required.

Abstract: A divider unit is provided for a high-radix division using a partial remainder. A quotient digit selecting device selects one from all quotient digits obtainable under an applied radix based on the signs and the upper digit values of the divisor and the partial remainder represented in the two's complement representation or, alternatively, on the upper digit values of the divisor and the partial remainder represented in the redundant binary representation. A number of divisor's multiple generating devices each generate at least one of 0 and a value obtained by multiplying the divisor with 2.sup.j (j=integer).