Abstract: A write PLL circuit generates a write clock signal for writing a video signal into a line memory. A readout PLL circuit generates a read clock signal for reading out the video signal stored in the line memory. An inner pincushion distortion correction voltage generation circuit modulates a correction waveform in the horizontal scanning period of time by a correction waveform in the vertical scanning period of time, to generate an inner pincushion distortion correction waveform, and adds a DC correction pulse to the inner pincushion distortion correction waveform and outputs the inner pincushion distortion correction waveform as an inner pincushion distortion correction voltage. A capacitive coupling circuit superimposes the inner pincushion distortion correction voltage on an output voltage of a loop filter of the readout PLL circuit, and feeds the inner pincushion distortion correction voltage to a VCO as a control voltage.

Abstract: A parallel scanning circuit outputs a parallel scanning signal for making forward and backward scanning lines parallel. A vertical correlation detection circuit detects a portion where the change in luminance in the vertical direction exceeds a predetermined value on the basis of a luminance signal, and outputs a movement control signal representing the distance of movement on the screen of the scanning line. A retrace period reversion circuit reverses the lime axis of the movement control signal in a retrace period. A clamping circuit clamps the movement control signal to a predetermined DC voltage at the timing of horizontal synchronizing signal. A synthesizing circuit synthesizes the parallel scanning signal and the movement control signal, and feeds a synthesized signal as a vertical velocity modulation signal to a vertical velocity modulation coil.

Abstract: A video signal conversion part of a horizontal deflection circuit deletes a prescribed number of horizontal scanning lines from a vertical blanking interval of an input video signal and assigns a time corresponding to the deleted horizontal scanning lines to horizontal blanking intervals of the remaining horizontal scanning lines thereby extending the horizontal blanking interval of each horizontal scanning line and outputting a video signal. A synchronizing signal separation circuit extracts a horizontal synchronizing signal and a vertical synchronizing signal from the video signal output from the video signal conversion part. An output part of the horizontal deflection circuit supplies a sawtooth horizontal deflection current to a horizontal deflection yoke in synchronization with the horizontal synchronizing signal output from the synchronizing signal separation circuit.

Abstract: An amplitude control circuit controls the amplitude of a correction signal periodically changing in a parabolic form at vertical scanning intervals based on the level of an amplitude control signal and applies an amplitude controlled output signal to an adder. The adder adds the amplitude controlled correction signal to the output signal of a low-pass filter and applies the resulting signal to a retrace scanning control circuit and a trace scanning control circuit. The retrace scanning control circuit and the trace scanning control circuit apply a gate pulse to horizontal output FETs.

Abstract: A video signal processing circuit synthesizes a video signal and a graphic signal on the basis of a display switching control signal, inverts a synthesized signal on the time axis for each of a forward scanning period and a backward scanning period, and output a display signal. A speed modulating signal control circuit inverts the binarized display switching control signal on the time axis for each of the forward scanning period and the backward scanning period, expands the pulse width thereof, and feeds the display switching control signal to a speed modulating signal generating circuit. The speed modulating signal generating circuit subjects a display signal to first-order differentiation, inverts the polarity of a differentiated signal in the backward scanning signal, sets a portion, corresponding to the graphic signal, in the differentiated signal on the basis of the display switching control signal at a zero level, and generates a speed modulating signal.

Abstract: A write PLL circuit generates a write clock signal for writing a video signal into a line memory. A readout PLL circuit generates a read clock signal for reading out the video signal stored in the line memory. An inner pincushion distortion correction voltage generation circuit modulates a correction waveform in the horizontal scanning period of time by a correction waveform in the vertical scanning period of time, to generate an inner pincushion distortion correction waveform, and adds a DC correction pulse to the inner pincushion distortion correction waveform and outputs the inner pincushion distortion correction waveform as an inner pincushion distortion correction voltage. A capacitive coupling circuit superimposes the inner pincushion distortion correction voltage on an output voltage of a loop filter of the readout PLL circuit, and feeds the inner pincushion distortion correction voltage to a VCO as a control voltage.

Abstract: A video signal conversion part of a horizontal deflection circuit deletes a prescribed number of horizontal scanning lines from a vertical blanking interval of an input video signal and assigns a time corresponding to the deleted horizontal scanning lines to horizontal blanking intervals of the remaining horizontal scanning lines thereby extending the horizontal blanking interval of each horizontal scanning line and outputting a video signal. A synchronizing signal separation circuit extracts a horizontal synchronizing signal and a vertical synchronizing signal from the video signal output from the video signal conversion part. An output part of the horizontal deflection circuit supplies a sawtooth horizontal deflection current to a horizontal deflection yoke in synchronization with the horizontal synchronizing signal output from the synchronizing signal separation circuit.

Abstract: A video signal converter converts a video signal to a required form. The required form of the signal is the display format for displaying the signal. The input signal is converted to a digital signal and stored in a memory using the output of a first clock pulse generator synchronized to the horizontal synchronizing signal of the input signal. The digital signal is read out from the memory using the output of a second clock pulse generator synchronized to the vertical synchronizing signal of the input signal from a position specified by the controller. The output digital signal is then reconverted to an analog signal.

Abstract: A television receiver comprising an information extracting circuit for extracting information from a format or content of an input video signal, a video signal processing circuit for processing this video signal by a program or data, a memory for storing the program and data, a CPU for controlling, operating or driving these elements, and a display device for displaying an image. The video signal processing circuit can, under the control of the CPU, decode the signal, correct or set the picture quality such as gradation and sharpness, or adaptively process an on-screen display based on the input video signal. The television receiver is also able to adaptively extend the functions of the television receiver corresponding to various signal formats.

Abstract: A wide-screen TV signal transmission apparatus includes transmitting a wide-screen TV signal generator for generating a wide-screen TV signal source; a scanning line converter for down-converting a wide-screen TV signal with an integer conversion ratio to obtain a conventional TV-compatible signal with upper and lower black bars; a vertical augmentation signal generator for generating a vertical augmentation signal to enhance the vertical resolution at the receiving side of the transmission apparatus; and adder for adding; a conventional TV-compatible signal and a vertical augmentation signal to obtain a conventional TV-compatible composed signal; and a transmitter for transmitting a conventional TV-compatible composed signal.

Abstract: A multiplex TV signal processing apparatus in a television signal transmitting and receiving system includes an apparatus at the transmitting side which has a first amplitude-modulator for modulating a first carrier by a main signal to obtain a vestigial side-band amplitude-modulated main signal; a second amplitude-modulator for modulating a second carrier but whose frequency is the same as which phase is 90 degree different from the first carrier by a sub signal to obtain a carrier suppressed amplitude-modulated signal; a first inserter for inserting a first ghost canceling reference signal into a horizontal line of the main signal during a vertical blanking period; a second inserter for inserting a second ghost canceling reference signal into the same horizontal line of the sub signal as the first ghost canceling reference signal; and includes an apparatus at the receiving side which has: a first demodulator for demodulating the main signal; a second demodulator for demodulating the sub signal; a ghost canc

Abstract: In the television broadcasting system called letter box method, it is proposed to transmit an image having a larger aspect ratio than that of the existing broadcasting system by using some of the scanning lines of the existing broadcasting system, and transmit some additional information signal in the remaining portion. An offset value applied to the additional information signal at the transmission side must be removed completely at the reception side. Accordingly, at the reception side, in the scanning line in which an offset reference signal indicative of the offset value is transmitted, the offset reference value and a DC level reference value of the scanning line are detected, and these values are retained until a next offset reference signal is detected.

Abstract: A television signal processor which is compatible with the existing television systems and is capable of producing television signals having a larger aspect ratio than the standard aspect ratio has an arrangement such that, at the transmission side, a main signal and a multiplex signal are produced from an electrical signal obtained by receiving an original image through processes such as time-axis compression, time-axis expansion, and chrominance signal processing, and are subjected to non-time-axis multiplexing. The processor has a further arrangement such that, at the reception side, there are provided a circuit for separating the non-time-axis multiplexed signal, a circuit for separating a luminance signal and a chrominance signal, a circuit for demodulating the chrominance signal, a circuit for effecting time-axis compression, a circuit for time-axis expanding the time-axis multiplexed signal, and a circuit for time-axis compressing the non-time-axis multiplexed signal.

Abstract: A main signal motion detection signal and a multiplex motion detection signal are processed to obtain a compensated motion detection signal. This signal is a motion detection signal for a portion other than a portion having an aspect ratio of 4:3. Thus, a television signal processor is provided which eliminates quality differences between images in the portion having an aspect ratio of 4:3 and images in the other portion having a different aspect ratio.

Abstract: A signal processing apparatus in a television signal transmitting system includes: a first group of delay lines for obtaining a first series of parallel signals; a first group of coefficient multipliers for weighting the first series of signals; a first adder for adding outputs of the first group of coefficient multipliers; a second group of delay lines for obtaining a second series of parallel signals; a second group of coefficient multipliers for weighting the second series of signals; a second adder for adding outputs of the second group of coefficient multipliers and one of the first series of signals; and a transmitter for transmitting output signals from the first and second adders.

Abstract: Disclosed are multiplex television signal processing apparatuses in a television signal transmitting and receiving system. An apparatus at the transmitting side comprises: a signal separator to separate a multiplex signal into a first and a second part; a time-multiplexer to time-multiplex a main television signal and the first part of the multiplex signal to obtain a time-multiplexed main signal; a first amplitude-modulator for modulating a first carrier by the multiplexed main signal to obtain a vestigial side band signal, amplitude-modulated main signal; a second amplitude-modulator for modulating a second carrier which is same in frequency as but different in phase by 90 degrees from the first carrier by a second multiplex signal; an inverse Nyquist filter for filtering this signal to obtain a vestigial side band, amplitude-modulated multiplex signal; and an adder for adding the vestigial side band, amplitude-modulated main and multiplex signals to obtain a multiplexed signal.

Abstract: In a multiplex signal processing apparatus, in the band of a demodulated signal in which a carrier is amplitude-modulated in a vestigial side band by a main signal, another carrier is superposed which is identical in frequency to the first carrier but different in phase by 90.degree. is amplitude-modulated its double side bands by a multiplex signal which is different from the main signal and which is formed into a vestigial side band signal by a nyquist filter. At least either the frequency or polarity of the multiplex signal is inverted on the transmission side by a multiplier, an oscillator and a filter. At least either the frequency or polarity of the multiplex signal is inverted on the reception side by a multiplier, an oscillator and a filter. The reception side has a crosstalk reduction filter for removing crosstalk from the main signal to the multiplex signal.