Patents by Inventor Hideyoshi Ito

Hideyoshi Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5094976
    Abstract: A dopant film contains an organic binder, an inorganic binder and a compound of an impurity element for diffusion. Both surfaces of the dopant film are coated with adhesive. Releasable sheets sandwich the dopant film. The dopant film permits automated alternate stacking with semiconductor wafers, providing an advantage of labor saving. When the alternate stacking is automated, it will become hard for the wafer breakage to occur, sharply decreasing the rate of breakage. Furthermore, since the adhesion of a semiconductor wafer improves, the variation in the diffusion depth will decrease.
    Type: Grant
    Filed: October 18, 1990
    Date of Patent: March 10, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaburo Iwabuchi, Hideyoshi Ito, Kenji Unetsubo
  • Patent number: 5073517
    Abstract: A dopant film contains an organic binder, an inorganic binder and a compound of an impurity element for diffusion. Both surfaces of the dopant film are coated with adhesive. Releasable sheets sandwich the dopant film. The dopant film permits automated alternate stacking with semiconductor wafers, providing an advantage of labor saving. When the alternate stacking is automated, it will become hard for the wafer breakage to occur, sharply decreasing the rate of breakage. Furthermore, since the adhesion of a semiconductor wafer improves, the variation in the diffusion depth will decrease. The semiconductor wafer manufacturing method includes the steps of impurity diffusion into both surfaces, dividing the wafer into two wafers in the direction of thickness, and polishing to a mirror surface each divided wafer opposite to the surface on which the impurity diffusion layer is formed. The material loss per wafer is reduced more than the conventional method due to the slicing into two wafers.
    Type: Grant
    Filed: October 18, 1990
    Date of Patent: December 17, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaburo Iwabuchi, Hideyoshi Ito, Kenji Unetsubo