Abstract: A disclosed reference-voltage generating circuit includes a supply voltage adjusting circuit for adjusting an external supply voltage Vcc and outputting predetermined constant voltages VA and VB; a first voltage supply circuit for generating a voltage Vpn that has a negative temperature coefficient by using the voltage VA; and a second voltage supply circuit for generating a voltage Vptat that has a positive temperature coefficient by using the voltage VB, and for generating the reference voltage Vref, which does not have a temperature coefficient, by adding Vpn and Vptat and thereby canceling the temperature coefficients.

Abstract: A temperature sensor comprises (a) a first voltage generating circuit that generates and outputs a first voltage having a positive or negative temperature coefficient in proportion to the absolute temperature; (b) a second voltage generating circuit that generates a second voltage having an opposite sign of temperature coefficient compared to the first voltage and outputs a reference voltage that does not have a temperature coefficient based on the second voltage; and (c) a comparator that compares the first voltage output from the first voltage generating circuit with the reference voltage output from the second voltage generating circuit.

Abstract: A charge/discharge protection circuit of the present invention includes a first terminal to which a negative electrode of a charger is connected and an internal detector unit which has an input connected to the first terminal, and prevents the variation of the threshold voltage of the input transistors in a short-circuit detector unit and in an overcurrent detector unit when the improper charger is connected to the battery for a long time. An improper charger detector unit outputs a detection signal when an improper charger is connected to the battery pack, in response to a voltage supplied to the first terminal by the improper charger.

Abstract: A general-use register set includes a plurality of registers in a central processing unit body. A register-bank memory has memory regions relevant to the plurality of registers and is connected to the central processing unit. An output signal of an address circuit included in the central processing unit is supplied to the register-bank memory. Alternatively, an output signal of a decoding circuit included in the central processing unit may be supplied to the register-bank memory. A signal for selecting either activation or deactivation of the register-bank memory is a signal which indicates a selection of the deactivation of the register-bank memory except in a case where data is written in the general-use register set and a case of a restoration operation after register bank switching.

Abstract: A general-use register set includes a plurality of registers in a central processing unit body. A register-bank memory has memory regions relevant to the plurality of registers and is connected to the central processing unit. An output signal of an address circuit included in the central processing unit is supplied to the register-bank memory. Alternatively, an output signal of a decoding circuit included in the central processing unit may be supplied to the register-bank memory. A signal for selecting either activation or deactivation of the register-bank memory is a signal which indicates a selection of the deactivation of the register-bank memory except in a case where data is written in the general-use register set and a case of a restoration operation after register bank switching.

Abstract: A semiconductor memory device having a small chip area is provided to reduce a manufacturing cost. The semiconductor memory device has memory unit comprising memory cells arranged in a matrix comprising n rows and m columns, where m.gtoreq.2 and n.gtoreq.1, each of the memory cells having a single port and being capable of storing a single word of data comprising at least one bit, the memory cells arranged in a single column forming a memory cell block. The semiconductor memory device selects one set of two memory cells, one from an arbitrary memory cell block and the other from a different memory cell block. A reading operation performed and a writing operation for the set of two memory cells are performed during the same cycle.

Abstract: A memory apparatus includes a memory cell array in which a plurality of memory cells are arranged in a matrix formation and divided into blocks, a writing part for serially writing data to the memory cell array through a set of writing bit lines, each of the writing bit lines connected to one of the blocks, a reading part for serially reading the data from the memory cells of the memory cell array through a set of reading bit lines, each of the reading bit lines connected to one of the blocks, and a set of precharging units each for presetting one of the reading bit lines to a prescribed voltage when data is read from one of the blocks of the memory cell array.

Abstract: A semiconductor integrated circuit apparatus has a basic cell region formed by arranging a plurality of basic cells each including a MOS transistor in longitudinal and transversal directions. The MOS transistor has source-drain section diffusive regions formed on a semiconductor substrate, and a gate electrode formed on a channel region between these source-drain section diffusive regions through a gate insulating film. One portion or all of the channel region of at least one MOS transistor within the basic cell region has an impurity concentration different from that in the channel region of another MOS transistor of the same conductivity type within the same basic cell. For example, a threshold voltage in the channel region of a MOS transistor is increased until about 6 volts by implanting ions into the channel region. No MOS transistor is operated at a power voltage such as 5 volts and separates MOS transistors on both sides thereof from each other.