Abstract: The present invention relates to a network connection apparatus for connecting a plurality of network terminals to an external network such as the Internet. In accordance with the present invention, there provides an easy-to-use network connection apparatus capable of building up an easy and flexible network system by providing the user with plurality types of interface. Specifically, the network connection apparatus comprises a first interface unit including at least one physical layer for connecting to an external network, a second interface unit including a plurality of physical layers for connecting to an internal network, and a controller for controlling the first interface unit and the second interface unit, wherein the second interface unit is capable of independent operation from the first interface unit, and the controller transmits and receives information between the first interface unit and second interface unit, and between the second interface units.

Abstract: A memory system having a semiconductor storage device divided into plural areas, in which information becomes accessible by specifying an absolute physical address, and a control section for controlling the semiconductor storage device is provided. The control section receives a designating signal for designating one area out of the plural areas of the semiconductor storage device and a relative physical address independent by each area and specifies the absolute physical address by adding an offset address corresponding to the area designated by the designating signal to the relative physical address so that the semiconductor storage device is accessed.

Abstract: Binary bit addresses for error detection designating the individual bits of multilevel memory cells for retaining two bits of data, respectively, are assigned so that pairs of the binary bit addresses corresponding to each of the memory cells are mutually exclusive in each digit. For each digit of the binary bit addresses, first parity codes including a parity code of data corresponding to all the binary bit addresses having “0” in the digit and a parity code of data corresponding to all the binary bit addresses having “1” in the digit are generated for both write data and read data. The presence of a memory cell storing erroneous data in both bits is detected when all the first parity codes of the read data are different from the first parity codes of the write data. Thus, the multilevel cell memory can perform reliable error detection/correction by a simple method.

Abstract: A method of marking an initial defective block in a semiconductor memory device having a memory area thereof divided into a plurality of blocks and provided with an ECC function includes the steps of detecting an initial defective block; and writing an ECC code causing an ECC error in a predetermined area of the initial defective block.

Abstract: In a memory card which includes a memory chip and a controller connected to the memory chip for the control of transferring a data from outside, the controller is provided with a buffer in which data is temporarily stored. In a first operation mode, the controller clears the data stored in the buffer after the data in the buffer is transferred to the memory chip. In a second operation mode, the controller does not clear the data stored in the buffer even after the data in the buffer is transferred to the memory chip. By the use of these modes, it becomes possible to write the data obtained by means of external transfer into the memory chip repeatedly for a plurality of times by means of internal transfer. Thus, it becomes unnecessary to repeat external transfer and internal transfer every time.

Abstract: A plurality of memory cells corresponding to an address space larger than 2n and smaller than 2(n+1), an invalid address detecting circuit, and an invalid signal outputting circuit are comprised. Upon command input, the invalid address detecting circuit invalidates a command in the case where the invalid address detecting circuit detects a fact that an address signal supplied from exterior indicates an invalid address space. Therefore, at the time of invalid address supply, internal circuits are not activated and an erroneous write or erase operation can be prevented. Since the internal circuits do not operate, power consumption can be reduced substantially. The invalid signal outputting circuit outputs an invalid signal by receiving the fact of invalid address signal detection by the invalid address detecting circuit. Therefore, a system unit mounting the semiconductor memory device can easily recognize that the invalid address signal has been supplied to the semiconductor memory device.

Abstract: A memory system having a semiconductor storage device divided into plural areas, in which information becomes accessible by specifying an absolute physical address, and a control section for controlling the semiconductor storage device is provided. The control section receives a designating signal for designating one area out of the plural areas of the semiconductor storage device and a relative physical address independent by each area and specifies the absolute physical address by adding an offset address corresponding to the area designated by the designating signal to the relative physical address so that the semiconductor storage device is accessed.

Abstract: A data buffer of a memory controller receives first program data, whose size is smaller than that of a page buffer, from a system, and holds the received data. A data adding circuit of the memory controller adds mask data to the first program data, to generate second program data whose size is equal to that of the page buffer. Since the mask data are not programmed to memory cells, only the first program data, which are supplied from the system, are programmed to pages of a nonvolatile semiconductor memory. Namely, even when the size of the page buffer of the nonvolatile semiconductor memory is large, it is possible to maintain interchangeability with an exiting system only by using the memory controller of the present invention.

Abstract: In a memory card which includes a memory chip and a controller connected to the memory chip for the control of transferring a data from outside, the controller is provided with a buffer in which data is temporarily stored. In a first operation mode, the controller clears the data stored in the buffer after the data in the buffer is transferred to the memory chip. In a second operation mode, the controller does not clear the data stored in the buffer even after the data in the buffer is transferred to the memory chip. By the use of these modes, it becomes possible to write the data obtained by means of external transfer into the memory chip repeatedly for a plurality of times by means of internal transfer. Thus, it becomes unnecessary to repeat external transfer and internal transfer every time.

Abstract: A base unit accommodates a radio terminal for making radio communications. This base unit has a recess for accommodating part of the radio terminal formed at least in two mutually orthogonal planes of the base unit body. An opening is formed at the inner side of the recess. Inside the base unit, a connector electrically connects and fixes the radio terminal. A rear part of the radio terminal is inserted through the opening. The base unit includes a lid for shielding the entire recess. The base unit body may include an external antenna connected to a cable having a terminal for connecting with an external antenna terminal provided in the radio terminal. This terminal may be disposed at a position corresponding to the external antenna terminal of the radio terminal of the lid. The base unit design is improved, invasion of foreign matter is prevented, and the radio reaching distance and directivity of the base unit are enhanced.

Abstract: A data buffer of a memory controller receives first program data, whose size is smaller than that of a page buffer, from a system, and holds the received data. A data adding circuit of the memory controller adds mask data to the first program data, to generate second program data whose size is equal to that of the page buffer. Since the mask data are not programmed to memory cells, only the first program data, which are supplied from the system, are programmed to pages of a nonvolatile semiconductor memory. Namely, even when the size of the page buffer of the nonvolatile semiconductor memory is large, it is possible to maintain interchangeability with an exiting system only by using the memory controller of the present invention.

Abstract: A memory system having a semiconductor storage device divided into plural areas, in which information becomes accessible by specifying an absolute physical address, and a control section for controlling the semiconductor storage device is provided. The control section receives a designating signal for designating one area out of the plural areas of the semiconductor storage device and a relative physical address independent by each area and specifies the absolute physical address by adding an offset address corresponding to the area designated by the designating signal to the relative physical address so that the semiconductor storage device is accessed.

Abstract: Binary bit addresses for error detection designating the individual bits of multilevel memory cells for retaining two bits of data, respectively, are assigned so that pairs of the binary bit addresses corresponding to each of the memory cells are mutually exclusive in each digit. For each digit of the binary bit addresses, first parity codes including a parity code of-data corresponding to all the binary bit addresses having “0” in the digit and a parity code of data corresponding to all-the binary bit addresses having “1” in the digit are generated for both write data and read data. The presence of a memory cell storing erroneous data in both bits is detected when all the first parity codes of the read data are different from the first parity codes of the write data. Thus, the multilevel cell memory can perform reliable error detection/correction by a simple method.

Abstract: Binary bit addresses for error detection designating the individual bits of multilevel memory cells for retaining two bits of data, respectively, are assigned so that pairs of the binary bit addresses corresponding to each of the memory cells are mutually exclusive in each digit. For each digit of the binary bit addresses, first parity codes including a parity code of data corresponding to all the binary bit addresses having “0” in the digit and a parity code of data corresponding to all the binary bit addresses having “1” in the digit are generated for both write data and read data. The presence of a memory cell storing erroneous data in both bits is detected when all the first parity codes of the read data are different from the first parity codes of the write data. Thus, the multilevel cell memory can perform reliable error detection/correction by a simple method.

Abstract: A method of marking an initial defective block in a semiconductor memory device having a memory area thereof divided into a plurality of blocks and provided with an ECC function includes the steps of detecting an initial defective block; and writing an ECC code causing an ECC error in a predetermined area of the initial defective block.