Abstract: Memory devices are disclosed. A memory device may include a memory array including a number of column planes and at least one circuit coupled to the memory array. The at least one circuit may generate test result data for a column address for each column plane of the number of column planes. The at least one circuit may further convert the test result data to a first result responsive to two or more of the column planes failing the test. The at least one circuit may also convert the test result data to a second result responsive to no column planes failing the test. Further, the at least one circuit may convert the test result data to a third result responsive to one column plane failing the test. The third result may identify the one column plane. Methods of testing a memory device, and electronic systems are also disclosed.

Abstract: Memory devices are disclosed. A memory device may include a memory array including a number of column planes and at least one circuit coupled to the memory array. The at least one circuit may generate test result data for a column address for each column plane of the number of column planes. The at least one circuit may further convert the test result data to a first result responsive to two or more of the column planes failing the test. The at least one circuit may also convert the test result data to a second result responsive to no column planes failing the test. Further, the at least one circuit may convert the test result data to a third result responsive to one column plane failing the test. The third result may identify the one column plane. Methods of testing a memory device, and electronic systems are also disclosed.

Abstract: The present invention relates to timing margin adjustment circuits using adjustable delay circuits. An example adjustable delay circuit may include a signal line, an output circuit, and a plurality of delay circuits. Each of the plurality of delay circuits may be configured to provide respective delay amounts that are different from each other, and where a first one of the plurality of delay circuits, which may be arranged most adjacently to the output circuit, being smaller in delay amount than other ones of the plurality of delay circuits. Each of the plurality of delay circuits may include an input node and an output node, and a selected one of the plurality of delay circuits connected at its input node to the signal line and at its output node to the output circuit, the rest of the plurality of delay circuits being disconnected from the signal line and the output circuit.

Abstract: The present invention relates to timing margin adjustment circuits using adjustable delay circuits. An example adjustable delay circuit may include a signal line, an output circuit, and a plurality of delay circuits. Each of the plurality of delay circuits may be configured to provide respective delay amounts that are different from each other, and where a first one of the plurality of delay circuits, which may be arranged most adjacently to the output circuit, being smaller in delay amount than other ones of the plurality of delay circuits. Each of the plurality of delay circuits may include an input node and an output node, and a selected one of the plurality of delay circuits connected at its input node to the signal line and at its output node to the output circuit, the rest of the plurality of delay circuits being disconnected from the signal line and the output circuit.

Abstract: The present invention relates to timing margin adjustment circuits using adjustable delay circuits. An example adjustable delay circuit may include a signal line, an output circuit, and a plurality of delay circuits. Each of the plurality of delay circuits may be configured to provide respective delay amounts that are different from each other, and where a first one of the plurality of delay circuits, which may be arranged most adjacently to the output circuit, being smaller in delay amount than other ones of the plurality of delay circuits. Each of the plurality of delay circuits may include an input node and an output node, and a selected one of the plurality of delay circuits connected at its input node to the signal line and at its output node to the output circuit, the rest of the plurality of delay circuits being disconnected from the signal line and the output circuit.

Abstract: The present invention relates to timing margin adjustment circuits using adjustable delay circuits. An example adjustable delay circuit may include a signal line, an output circuit, and a plurality of delay circuits. Each of the plurality of delay circuits may be configured to provide respective delay amounts that are different from each other, and where a first one of the plurality of delay circuits, which may be arranged most adjacently to the output circuit, being smaller in delay amount than other ones of the plurality of delay circuits. Each of the plurality of delay circuits may include an input node and an output node, and a selected one of the plurality of delay circuits connected at its input node to the signal line and at its output node to the output circuit, the rest of the plurality of delay circuits being disconnected from the signal line and the output circuit.

Abstract: Disclosed herein is a device that comprises a delay line delaying a first clock signal in response to the delay control information to produce a delayed clock signal, a phase detector unit controls the delay control information in response to a relationship in phase between the first clock signal and a second clock signal, and an inverting control unit receiving the delayed clock signal and producing a third clock signal, the second clock signal being produced in response to the third clock signal. The third clock signal is in phase with the delayed clock signal when the inverting control unit is in a first state and complementary to the delayed clock signal when the inverting control unit is in a second state.

Abstract: The semiconductor device includes a frequency detection circuit that outputs a frequency detection signal based on a frequency of a first clock signal; a phase comparison circuit that compares a phase of the first clock signal with a phase of a reference clock signal and outputs a phase comparison signal according to a result of the comparison; and a phase adjustment circuit that outputs a second clock signal by shifting the phase of the first clock signal according to the phase comparison signal. An amount of the phase of the first clock signal according to the phase comparison signal is variable according to the frequency detection signal.

Abstract: Disclosed herein is a device that comprises a delay line delaying a first clock signal in response to the delay control information to produce a delayed clock signal, a phase detector unit controls the delay control information in response to a relationship in phase between the first clock signal and a second clock signal, and an inverting control unit receiving the delayed clock signal and producing a third clock signal, the second clock signal being produced in response to the third clock signal. The third clock signal is in phase with the delayed clock signal when the inverting control unit is in a first state and complementary to the delayed clock signal when the inverting control unit is in a second state.