Patents by Inventor Hideyuki Ichiyama

Hideyuki Ichiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5900582
    Abstract: A leadframe for producing a semiconductor device having a lead-on chip (LOC) structure with leads extending across a semiconductor chip, the leadframe includes a frame for a die pad having an outer frame section, a die pad displaced from the outer frame section, and a suspending lead connecting the die pad to the outer frame section with the die pad disposed inside the outer frame section; and a frame for leads including an outer frame portion and leads extending from opposite sides of the outer frame portion, connected to the frame for a die pad, the die pad being connected to the frame for leads at the suspending lead, wherein one of the frame for a die pad and the frame for leads includes a projection and the other of the frame for a die pad and the frame for leads includes a hole, the hole receiving the projection, the projection being disposed parallel to the frame for leads, connecting the frame for a die pad to the frame for leads.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: May 4, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshihiro Tomita, Naoto Ueda, Yoshirou Nishinaka, Shunichi Abe, Hideyuki Ichiyama
  • Patent number: 5814883
    Abstract: A semiconductor device includes a substrate having a recess; a semiconductor chip disposed in the recess; a plurality of external electrodes disposed on the substrate; a lid covering the recess; and a heat radiator disposed between the semiconductor chip and the substrate for transmitting heat generated by the semiconductor chip to the substrate for radiation.
    Type: Grant
    Filed: May 1, 1996
    Date of Patent: September 29, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Eengineering Corporation
    Inventors: Akiyoshi Sawai, Kisamitsu Ono, Hideyuki Ichiyama, Katsunori Asai
  • Patent number: 5763829
    Abstract: A high-reliability semiconductor device and a method of producing the device. Absorption of moisture into a semiconductor device is effectively avoided by using a hard solder material, such as common solder having no moisture absorption, for die-bonding a semiconductor chip to a die pad. Thus, in the semiconductor device in accordance with the present inventions there are no corrosion problems nor package-cracking due to absorbed moisture.
    Type: Grant
    Filed: July 25, 1995
    Date of Patent: June 9, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshihiro Tomita, Naoto Ueda, Yoshirou Nishinaka, Shunichi Abe, Hideyuki Ichiyama
  • Patent number: 5724726
    Abstract: A method of making a semiconductor device having a lead-on-chip structure includes bending a die pad extending from an outer frame outwardly from the outer frame. Thereafter, with the die pad in a convenient position, a semiconductor chip is die-bonded to the die pad. Thereafter, the die pad is bent back toward the outer frame so that it is generally parallel to but spaced from the outer frame with leads extending from the outer frame being generally parallel to the semiconductor chip. Electrodes of the semiconductor chip are connected by wire-bonding to the leads extending from the outer frame. After resin molding, the outer frame lying outside the resin package is severed and removed, completing the lead-on-chip semiconductor device.
    Type: Grant
    Filed: March 13, 1996
    Date of Patent: March 10, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshihiro Tomita, Naoto Ueda, Yoshirou Nishinaka, Shunichi Abe, Hideyuki Ichiyama
  • Patent number: 5592019
    Abstract: A semiconductor device in a vertical surface mount package, reduced in size and having a higher heat radiating capacity, a method of producing the semiconductor device, and a semiconductor module. Leads of a first lead frame and leads of a second lead frame are parallel to each other and at least a portion of the leads overlap leads of the other lead frame when geometrically projected on them. An inner lead may extend out from the semiconductor package or the back side of a die pad in the semiconductor package may be exposed. The invention allows more outer leads to be used and makes it possible to reduce the size of the semiconductor device and to achieve high density mounting.
    Type: Grant
    Filed: April 4, 1995
    Date of Patent: January 7, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Ueda, Kisamitsu Ono, Kou Shimomura, Hideyuki Ichiyama
  • Patent number: 5535509
    Abstract: A semiconductor device including a lead on chip structure employs two frames. One of the frames includes a die pad and an outer frame portion and the other frame includes a plurality of leads and an outer lead portion. After a semiconductor chip is die bonded to the die pad, the two frames are connected to each other with the leads extending across the semiconductor chip. Slits within the second frame provide access to parts of the outer frame of the first frame and the first frame is severed at those slits. The severed portions of the first frame are removed after which the leads of the second frame are connected by wire bonding to the semiconductor chip. Finally, the semiconductor chip, the remaining part of the first frame, and the second frame are encapsulated in a resin with leads extending from the resin. The remaining parts of the outer frame of the second frame are removed by cutting and the exposed leads outside the resin are formed into a desired shape.
    Type: Grant
    Filed: October 19, 1994
    Date of Patent: July 16, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshihiro Tomita, Naoto Ueda, Yoshirou Nishinaka, Shunichi Abe, Hideyuki Ichiyama
  • Patent number: 5372295
    Abstract: A solder material comprises a first solder plate and a second solder plate having a thickness equal to or larger than 1 micron provided at the both surfaces of the first solder plate comprising material having a lower melting point than the first solder or material which reacts with the first solder to produce an alloy having a lower melting point than the first solder.A junctioning method comprises putting the above-described solder material inserted between two objects to be junctioned to each other; heating the solder material to a temperature higher than the melting point of the second solder or the alloy and lower than the melting point of said first solder thereby to melt the second solder or the alloy; and thereafter cooling or keeping the solder material at a temperature in the vicinity of the melting point thereby to junction the objects to be junctioned to each other.
    Type: Grant
    Filed: October 1, 1992
    Date of Patent: December 13, 1994
    Assignee: Ryoden Semiconductor System Engineering Corporation
    Inventors: Shunichi Abe, Katunori Asai, Yoshihiro Tomita, Hideyuki Ichiyama, Seizou Ohumae, Yoshirou Nishinaka, Katsuyuki Fukutome, Naoto Ueda, Toshio Takeuchi
  • Patent number: 5373190
    Abstract: A resin-sealed semiconductor device includes and has a size that is substantially the same as a semiconductor element. The semiconductor device is easily handled and highly reliable. First ends of terminals made of a conductor, such as copper or the like, are respectively electrically connected to corresponding electrodes of the semiconductor element. The semiconductor element is sealed with a sealing resin so that second ends of the terminals are exposed at the surface of the sealing resin. Since the terminals are strong and are not easily damaged, there are no voids and a highly reliable semiconductor device is achieved.
    Type: Grant
    Filed: February 27, 1992
    Date of Patent: December 13, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hideyuki Ichiyama
  • Patent number: 5207102
    Abstract: A semiconductor pressure sensor is manufactured by integrally encapsulating a semiconductor pressure, sensor chip, a pedestal, leads, wires and a die pad in an outer package except for the surface of a diaphragm of the semiconductor pressure sensor chip and the reverse side of the die pad. The ratio of the thickness of the pedestal to the thickness of the semiconductor pressure sensor chip is 7.5 or less, while the ratio of the diameter of an opening formed in the outer package at the surface of the diaphragm and the diameter of the diaphragm is 1 or more. The thermal stress generated in the semiconductor pressure sensor chip can freely be reduced to a desired value, and a semiconductor pressure sensor exhibiting a desired accuracy can therefore be obtained. Furthermore, since the semiconductor pressure sensor can be manufactured by an ordinary IC manufacturing process, a semiconductor pressure sensor with reduced cost and having high quality can be produced.
    Type: Grant
    Filed: September 20, 1991
    Date of Patent: May 4, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshiharu Takahashi, Tetsuya Hirose, Hideyuki Ichiyama
  • Patent number: 4974052
    Abstract: A plastic packaged semiconductor device includes a semiconductor chip with electrodes formed on the surface thereof, a package body made of resin molded to the semiconductor chip, and an adhesion improving film formed on those portions of the surface of the semiconductor chip which surround the electrodes for enhancing the adhesion of the semiconductor chip to the package body.
    Type: Grant
    Filed: December 14, 1988
    Date of Patent: November 27, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hideyuki Ichiyama