Abstract: An OR circuit (34, 35) OR-operates an emulator reset signal (106, 107) based on a reset instruction from an emulator (30) and an external reset signal (115, 116) supplied from an external reset generation circuit. The OR operation result is distributed and supplied to a processor (10) and a companion chip (20) as a system reset signal (109, 110), thereby initializing both chips of the processor (10) and the companion chip (20) in accordance with the reset the emulator (30).

Abstract: An arithmetic operation unit for operating according to pipeline control and an instruction decoder for controlling the arithmetic operation unit by decoding an instruction, including a state retaining unit for retaining a state of the operation of the arithmetic operation unit, wherein the instruction decoder controls the execution of the arithmetic operation unit according to the information stored by the state retaining unit. A state is set when the decoder issues a signal for starting the arithmetic operation unit and the state is cleared when the decoder issues a signal for stopping the operation of the arithmetic operation unit. The arithmetic operation unit further comprises a unit for obtaining a maximum and a minimum value with a simple construction. A multiplier of the arithmetic operation unit comprises a unit for performing an addition of an exponential part of a multiplier and that of a multiplicand with a simple construction.

Abstract: A memory accessing device and method, in a data processing system which has pipelines, for correctly associating prefetched addresses from an address bus with corresponding prefetched data from a data bus, when sending data to and receiving data from an external memory. The memory accessing device has a condition determining device determining pipeline control conditions based on pipeline information and address information; a number-of-stages selecting device selecting the number of pipeline stages based on pipeline activation conditions and the pipeline control conditions; and a valid data detecting device detecting valid data positions in the prefetched data based on the number of pipeline stages selected and correctly associating the valid data positions in the prefetched data with the prefetched addresses.

Abstract: A memory access device including a memory unit having a plurality of independently accessible banks and a pipeline stage number setting unit for setting the number of the pipeline stages in a pipeline operation for accessing the next-to-be-accessed one of the plurality of independently accessible banks before completing an access to a currently accessed one of the plurality of independently accessible banks. The number of banks accessed is not more than the number of the plurality of banks. A unit is provided for generating an address of the next-to-be-accessed one of the plurality of independently accessible banks and for switching a bank from the currently used one of the plurality of independently accessible banks to the next-to-be-accessed one of the plurality of independently accessible banks in accordance with the number of the pipeline stages set by the pipeline stage number setting unit.

Abstract: A processor comprises a command storage unit for storing a plurality of commands and data received from outside the processor, a command interpreter for interpreting commands and data stored in the command storage unit, an address designator for designating a particular execution address of the storage unit according to a command interpreted by the command interpreter or to an operation start command, and an update selector for selecting whether or not to update the value of an execution address designated by the address designator according to a command interpreted by the command interpreter.

Abstract: A slave processor for executing for example a vector operation is connected to a master processor. A vector length for a vector operation set to the slave processor can be changed without intervention of the master processor. When the master processor activates the slave processor, the slave processor outputs a busy signal immediately (at most one cycle later). The master processor reads the value of a busy register representing a busy/ready status of the slave processor in a slave access cycle at highest speed (in two cycles at most). Regardless of whether the master processor and the slave processor was designed as series products or general purpose products, they can be effectively connected.

Abstract: A system comprising a cache memory connected to a processor and a main memory wherein the processor has a unit for outputting a discrimination signal that indicates whether the access to said cache memory is a sequential address data access or a non-sequential address data access, and the cache memory has a unit for changing the processing in a cache-miss state based on the output discrimination signal. In the case of the non-sequential address data access, unnecessary access to the main memory is suppressed to reduce the penalty in the cache-miss state and, hence, to improve the efficiency of the whole system by realizing a high-speed operation.

Abstract: A memory accessing device is connected to a central processing unit and a memory unit via a common bus. The memory accessing device accesses the memory unit independently of the central processing unit. The device includes an address generating unit for generating an address, an address control unit for outputting the generated address to the bus, and a control unit for controlling the address control unit to suspend or terminate memory access controlled in an address pipeline mode when the memory accessing device internally or externally issues a request for the suspension or the termination of the memory access controlled in the address pipeline mode. The control unit terminates or suspends the memory access when it receives a request internally or externally of the memory accessing device for the suspension or the termination of the memory access.

Abstract: A processor includes a register file unit for storing operands and operation results, operation units for performing operations on the operands and writing operation results into the register file unit in a normal operation mode, and a random number generator for generating random numbers and outputting, instead of the operands, the random numbers to the operation units in a test mode. Further, the processor includes a selector part for selecting the operands from the register file unit in the normal operation mode and selecting the random numbers generated by the random number generator in the test mode, the operands or the random numbers selected by said selector being applied to the operation units.

Abstract: An index buffer circuit and a translation look-aside buffer (TLB) are provided in an address unit of a vector processor unit. The index buffer circuit incudes a plurality of buffers, an input pointer generating unit for generating an input control signal indicating which selected buffer in a buffer portion, index data shall be stored, and an output pointer generating unit for outputting a control signal indicated from which selected buffer in the buffer portion output data is to be read. The TLB translates a logical address to a physical address upon receipt of the output from the index buffer. The TLB has a least recently used (LRU) flag register which can maintain the priority even if the entries are reset and thus the entries of the TLB can be used as buffers when the vector processor unit operates as a bus slave.

Abstract: A memory access system employs a pipe-line process in which access can be carried out for a microprocessor using one cycle of two clocks and for a microprocessor using one cycle of one clock. Access speed of a main memory can be considerably improved ensuring applicability in general use. A transition request signal to a pipe-line is received, a control signal that continues as long as the cycle number corresponding to at least the address first-out number of the pipe-line immediately after the start of the pipe-line operation is produced. Concurrently, a data complete signal indicating the completion of data access for a bank is produced during the time that either of the above two signals is also generating an address latch signal synchronized to a clock signal and routed to respective banks, for executing high speed data access.

Abstract: A memory accessing device is coupled to a first bus which connects a first buffer storage unit in a central processing unit to a second buffer storage unit. The memory accessing device can access, through the first bus, at least one of the first buffer storage unit and the second buffer storage unit independently of the central processing unit. The memory accessing device includes an address generating circuit for generating an address to access either or both of the first buffer storage unit and the second buffer storage unit. An output control unit in the memory accessing device outputs the address generated by the address generating circuit to the first bus. An output of the control unit enter an idle state if the second buffer storage unit issues a request for access to the first buffer storage unit when the memory accessing device obtains a right to use the first bus.

Abstract: A bus controller reduces the bus access wait time, to improve the performance of a processing unit that frequently accesses a main storage. The bus controller comprises a request signal generation unit for generating a bus right request signal according to a request from the processing unit, a bus right arbitration unit for arbitrating a bus right in response to the bus right request signal and importing the result of the arbitration, a bus access unit for accessing a bus through the processing unit serving as a bus master in response to a bus right acquisition acknowledgement, and a hold instruction unit for holding the request signal while a predetermined hold signal is being asserted and a predetermined release signal is being negated.

Abstract: A direct memory access (DMA) controller is adaptable to control a DMA which is independently made in a plurality of channels of a data processing apparatus, where the plurality of channels have predetermined priority sequences and the DMA controller includes a bus and terminal controller coupled to a system bus for obtaining a right to use the system bus responsive to a transfer request, an interrupt and slave controller coupled to the system bus for controlling an interrupt which is made to a central processing unit (CPU) when a data transfer ends for each of the plurality of channels and for controlling an access from the CPU, and an operation determination part for determining an operation of the DMA controller depending on the transfer request, whether or not the bus and terminal controller obtained the right to use the system bus and whether or not the access is made from the CPU.

Abstract: A semiconductor integrated circuit device includes an internal logic circuit for carrying out a logic operation and generating an output signal based on the logic operation, and an output buffer circuit connected to the internal logic circuit, for outputting the output signal through an output terminal in synchronism with a clock signal. The semiconductor integrated circuit also includes a non-overlap clock generator, and a third-clock generator. The non-overlap clock generator generates a first internal clock signal which falls in synchronism with a falling edge of an external clock signal, and generates a second internal clock signal which falls in synchronism with a rising edge of the external clock signal, the internal logic circuit carrying out the logic operation in synchronism with the first and second internal clock signals.

Abstract: An integrated circuit receiving an input signal and producing output signal including: a set/reset circuit, operatively connected to an internal main circuit, being set in response to the first signal and reset in response to the second signal in a normal mode; an output buffer circuit, connected to the set/reset circuit, for producing the output signal in response to an output of the set/reset circuit; and a control circuit, connected between the internal main circuit and the set/reset circuit, receiving the first signal, a reset signal for initializing the internal main circuit, the first signal, the second signal, and a first test signal, during a DC test mode, the control circuit resetting the set/reset circuit in response to a receipt of the reset signal regardless of the second signal and setting the set/reset circuit in response to a receipt of the first test signal regardless of the reset signal and the first signal.