Patents by Inventor Hideyuki Inotsume

Hideyuki Inotsume has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10535585
    Abstract: In one general aspect, an integrated passive device (IPD) die includes at least one passive component that is embedded in an insulator material disposed on a front surface of a substrate. The IPD die includes a through-substrate via (TSV) extending from the backside of the substrate toward the front surface of the substrate. The TSV defines interconnect access to at least one passive component embedded in the insulator material disposed on the front surface of the substrate. The substrate has a thickness less than three-quarters of an original thickness of the substrate.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: January 14, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Takashi Noma, Hideyuki Inotsume, Kazuo Okada
  • Publication number: 20190067164
    Abstract: In one general aspect, an integrated passive device (IPD) die includes at least one passive component that is embedded in an insulator material disposed on a front surface of a substrate. The IPD die includes a through-substrate via (TSV) extending from the backside of the substrate toward the front surface of the substrate. The TSV defines interconnect access to at least one passive component embedded in the insulator material disposed on the front surface of the substrate. The substrate has a thickness less than three-quarters of an original thickness of the substrate.
    Type: Application
    Filed: November 15, 2017
    Publication date: February 28, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Takashi NOMA, Hideyuki INOTSUME, Kazuo OKADA
  • Patent number: 7554183
    Abstract: A semiconductor device having a plurality of semiconductor chips mounted on lead frames is miniaturized by reducing its planar size and thickness. By disposing a rear surface of a first island and a top surface of a second island so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: June 30, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hideyuki Inotsume, Hirokazu Fukuda
  • Patent number: 7535087
    Abstract: By disposing a rear surface of a first island 12 and a top surface of a second island 13 so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip 20 are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: May 19, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hideyuki Inotsume, Hirokazu Fukuda
  • Publication number: 20080203582
    Abstract: A semiconductor device having a plurality of semiconductor chips mounted on lead frames is miniaturized by reducing its planar size and thickness. By disposing a rear surface of a first island and a top surface of a second island so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.
    Type: Application
    Filed: September 26, 2007
    Publication date: August 28, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Hideyuki Inotsume, Hirokazu Fukuda
  • Publication number: 20070228537
    Abstract: By disposing a rear surface of a first island 12 and a top surface of a second island 13 so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip 20 are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.
    Type: Application
    Filed: March 28, 2007
    Publication date: October 4, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Hideyuki Inotsume, Hirokazu Fukuda
  • Patent number: 6833608
    Abstract: Two different switches with two different signal input schemes are fabricated by mounting the same semiconductor chip on the same lead pattern. Two of the leads of the lead pattern provides space enough for wire-bonding connection to corresponding electrode pads on the semiconductor chip at both ends of the semiconductor chip. Because each of electrode pads can be connected to the corresponding lead at either end of the semiconductor chip, two sets of bonding wire connection between the leads and the electrode pads provides two different switches with two different signal inputs scheme.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: December 21, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Mikito Sakakibara, Hideyuki Inotsume, Haruhiko Sakai, Shigeo Kimura
  • Patent number: 6833616
    Abstract: A semiconductor chip is mounted on a wiring board that has a two-layer lead structure. One of the leads used for receiving input signals is disposed on the lower layer and runs underneath the semiconductor chip forming an U-shaped wiring line while other leads are disposed on the upper layer. Because one of the upper layer leads for receiving input signals is disposed in the U-shaped pocket of the U-shaped wiring line of the lower layer, the relative positioning of corresponding terminals can be changed into a reversal of the positioning of the electrode pads of the chip connected to the terminals. Furthermore, one of the upper layer lead for receiving control signals is placed between the chip and the lower layer lead underneath the chip to prevent high frequency signal interference.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: December 21, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Mikito Sakakibara, Hideyuki Inotsume, Haruhiko Sakai, Shigeo Kimura
  • Patent number: 6818969
    Abstract: A semiconductor device includes four input terminals, four leads extending from the corresponding input terminals and a semiconductor chip that has a first circuit and a second circuit and is mounted on one of the leads. The lead having the semiconductor chip thereon bends in a plane of the substrate so that an end portion and a mid portion of the lead are exposed on one side of the semiconductor chip. One of the input electrode pads of the first circuit is connected to the end portion of the lead by a bonding wire. The end portion of the lead is on the opposite side of the mid portion of the lead with respect to one of the leads that is connected to one of the input electrode pads of the second circuit by a bonding wire. This configuration achieves a crossing wiring structure within the packaging. By changing the connection of bonding wires, the crossing wiring structure is easily undone.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: November 16, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Mikito Sakakibara, Hideyuki Inotsume, Haruhiko Sakai, Shigeo Kimura
  • Publication number: 20030151137
    Abstract: A semiconductor chip is mounted on a wiring board that has a two-layer lead structure. One of the leads used for receiving input signals is disposed on the lower layer and runs underneath the semiconductor chip forming an U-shaped wiring line while other leads are disposed on the upper layer. Because one of the upper layer leads for receiving input signals is disposed in the U-shaped pocket of the U-shaped wiring line of the lower layer, the relative positioning of corresponding terminals can be changed into a reversal of the positioning of the electrode pads of the chip connected to the terminals. Furthermore, one of the upper layer lead for receiving control signals is placed between the chip and the lower layer lead underneath the chip to prevent high frequency signal interference.
    Type: Application
    Filed: December 5, 2002
    Publication date: August 14, 2003
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Mikito Sakakibara, Hideyuki Inotsume, Haruhiko Sakai, Shigeo Kimura
  • Publication number: 20030137044
    Abstract: Two different switches with two different signal input schemes are fabricated by mounting the same semiconductor chip on the same lead pattern. Two of the leads of the lead pattern provides space enough for wire-bonding connection to corresponding electrode pads on the semiconductor chip at both ends of the semiconductor chip. Because each of electrode pads can be connected to the corresponding lead at either end of the semiconductor chip, two sets of bonding wire connection between the leads and the electrode pads provides two different switches with two different signal inputs scheme.
    Type: Application
    Filed: November 15, 2002
    Publication date: July 24, 2003
    Inventors: Tetsuro Asano, Mikito Sakakibara, Hideyuki Inotsume, Haruhiko Sakai, Shigeo Kimura
  • Publication number: 20030094679
    Abstract: A semiconductor device includes four input terminals, four leads extending from the corresponding input terminals and a semiconductor chip that has a first circuit and a second circuit and is mounted on one of the leads. The lead having the semiconductor chip thereon bends in a plane of the substrate so that an end portion and a mid portion of the lead are exposed on one side of the semiconductor chip. One of the input electrode pads of the first circuit is connected to the end portion of the lead by a bonding wire. The end portion of the lead is on the opposite side of the rmid portion of the lead with respect to one of the leads that is connected to one of the input electrode pads of the second circuit by a bonding wire. This configuration achieves a crossing wiring structure within the packaging. By changing the connection of bonding wires, the crossing wiring structure is easily undone.
    Type: Application
    Filed: October 30, 2002
    Publication date: May 22, 2003
    Inventors: Tetsuro Asano, Mikito Sakakibara, Hideyuki Inotsume, Haruhiko Sakai, Shigeo Kimura