Abstract: A semiconductor device provided with a first node to which a first power supply potential is supplied, a second node to which a second power supply potential lower than the first power supply potential is supplied, a signal terminal configured to be used in order to at least output a signal, an output driver including a first output element configured to supply the first power supply potential to the signal terminal when in an ON state, and a second output element provided in a P-well electrically separated from a semiconductor substrate and configured to supply the second power supply potential to the signal terminal when in an ON state, and a switch circuit configured to selectively supply a potential to the P-well, according to at least a potential of the signal terminal.

Abstract: A semiconductor device provided with a first node to which a first power supply potential is supplied, a second node to which a second power supply potential lower than the first power supply potential is supplied, a signal terminal configured to be used in order to at least output a signal, an output driver including a first output element configured to supply the first power supply potential to the signal terminal when in an ON state, and a second output element provided in a P-well electrically separated from a semiconductor substrate and configured to supply the second power supply potential to the signal terminal when in an ON state, and a switch circuit configured to selectively supply a potential to the P-well, according to at least a potential of the signal terminal.

Abstract: Provided is a semiconductor integrated circuit device including: an output buffer circuit having a P channel transistor connected between a first power supply terminal and a signal terminal; a potential control circuit that supplies potential from the first power supply terminal or the signal terminal to a back gate of the P channel transistor according to the potential of the signal terminal; a first protection diode having an anode connected to the signal terminal; a common discharge line connected to a cathode of the first protection diode; an electrostatic discharge protection circuit connected between the common discharge line and a second power supply terminal; and a second protection diode having an anode connected to the second power supply terminal and a cathode connected to the signal terminal.

Abstract: Provided is a semiconductor integrated circuit device including: an output buffer circuit having a P channel transistor connected between a first power supply terminal and a signal terminal; a potential control circuit that supplies potential from the first power supply terminal or the signal terminal to a back gate of the P channel transistor according to the potential of the signal terminal; a first protection diode having an anode connected to the signal terminal; a common discharge line connected to a cathode of the first protection diode; an electrostatic discharge protection circuit connected between the common discharge line and a second power supply terminal; and a second protection diode having an anode connected to the second power supply terminal and a cathode connected to the signal terminal.

Abstract: A semiconductor integrated circuit that operates on multiple supply potentials including a first potential and a second potential that is higher than the first potential. The semiconductor integrated circuit includes a potential-lowering circuit operating on the second supply potential and including an N-channel MOS transistor that lowers the second supply potential applied to a gate thereof to output a lowered potential from a source thereof, a judging circuit operating on the potential outputted from the potential-lowering circuit and judging whether the first supply potential is high-level or low-level, and a buffer circuit outputting a control signal showing whether the first supply potential is fed based on judgment outputted from the judging circuit.

Abstract: A semiconductor integrated circuit that operates on multiple supply potentials including a first potential and a second potential that is higher than the first potential. The semiconductor integrated circuit includes a potential-lowering circuit operating on the second supply potential and including an N-channel MOS transistor that lowers the second supply potential applied to a gate thereof to output a lowered potential from a source thereof, a judging circuit operating on the potential outputted from the potential-lowering circuit and judging whether the first supply potential is high-level or low-level, and a buffer circuit outputting a control signal showing whether the first supply potential is fed based on judgment outputted from the judging circuit.