Patents by Inventor Hideyuki Kamata
Hideyuki Kamata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230209829Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: ApplicationFiled: March 1, 2023Publication date: June 29, 2023Inventors: Toshifumi MINAMI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA, Hideyuki KAMATA, Teppei HIGASHITSUJI
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Patent number: 11621278Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: GrantFiled: March 22, 2022Date of Patent: April 4, 2023Assignee: Kioxia CorporationInventors: Toshifumi Minami, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara, Hideyuki Kamata, Teppei Higashitsuji
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Publication number: 20220216232Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: ApplicationFiled: March 22, 2022Publication date: July 7, 2022Inventors: Toshifumi MINAMI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA, Hideyuki KAMATA, Teppei HIGASHITSUJI
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Patent number: 11315950Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: GrantFiled: September 15, 2020Date of Patent: April 26, 2022Assignee: KIOXIA CORPORATIONInventors: Toshifumi Minami, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara, Hideyuki Kamata, Teppei Higashitsuji
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Publication number: 20200411551Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: ApplicationFiled: September 15, 2020Publication date: December 31, 2020Inventors: Toshifumi MINAMI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA, Hideyuki KAMATA, Teppei HIGASHITSUJI
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Patent number: 10818691Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: GrantFiled: September 13, 2019Date of Patent: October 27, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Toshifumi Minami, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara, Hideyuki Kamata, Teppei Higashitsuji
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Publication number: 20200006382Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: ApplicationFiled: September 13, 2019Publication date: January 2, 2020Inventors: Toshifumi MINAMI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA, Hideyuki KAMATA, Teppei HIGASHITSUJI
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Patent number: 10461093Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: GrantFiled: February 12, 2018Date of Patent: October 29, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Toshifumi Minami, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara, Hideyuki Kamata, Teppei Higashitsuji
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Publication number: 20180175055Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: ApplicationFiled: February 12, 2018Publication date: June 21, 2018Inventors: Toshifumi MINAMI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA, Hideyuki KAMATA, Teppei HIGASHITSUJI
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Patent number: 9893078Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: GrantFiled: February 24, 2015Date of Patent: February 13, 2018Assignee: Toshiba Memory CorporationInventors: Toshifumi Minami, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara, Hideyuki Kamata, Teppei Higashitsuji
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Patent number: 9768189Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.Type: GrantFiled: April 7, 2016Date of Patent: September 19, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroshi Shinohara, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Toshifumi Minami, Hiroyuki Maeda, Shinji Saito, Hideyuki Kamata
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Patent number: 9437300Abstract: A semiconductor memory device includes first and second memory cell transistors, first and second word lines electrically connected to the first and second memory cell transistors, respectively, first and second transfer transistors. The first and second transistors are electrically connected to the first and second word lines, respectively. The sizes of the first transistor and the second transistor are different.Type: GrantFiled: August 26, 2014Date of Patent: September 6, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hideyuki Kamata, Toshifumi Minami, Teppei Higashitsuji, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara
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Publication number: 20160218109Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.Type: ApplicationFiled: April 7, 2016Publication date: July 28, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi SHINOHARA, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Toshifumi Minami, Hiroyuki Maeda, Shinji Saito, Hideyuki Kamata
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Patent number: 9337145Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.Type: GrantFiled: March 10, 2015Date of Patent: May 10, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Shinohara, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Toshifumi Minami, Hiroyuki Maeda, Shinji Saito, Hideyuki Kamata
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Publication number: 20160071870Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: ApplicationFiled: February 24, 2015Publication date: March 10, 2016Inventors: Toshifumi MINAMI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA, Hideyuki KAMATA, Teppei HIGASHITSUJI
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Publication number: 20160071793Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.Type: ApplicationFiled: March 10, 2015Publication date: March 10, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi SHINOHARA, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Toshifumi MINAMI, Hiroyuki MAEDA, Shinji SAITO, Hideyuki KAMATA
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Publication number: 20150262669Abstract: A semiconductor memory device includes first and second memory cell transistors, first and second word lines electrically connected to the first and second memory cell transistors, respectively, first and second transfer transistors. The first and second transistors are electrically connected to the first and second word lines, respectively. The sizes of the first transistor and the second transistor are different.Type: ApplicationFiled: August 26, 2014Publication date: September 17, 2015Inventors: Hideyuki KAMATA, Toshifumi MINAMI, Teppei HIGASHITSUJI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA
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Publication number: 20150062843Abstract: According to one embodiment, a semiconductor device includes a cell portion and a peripheral portion, including: a substrate, a first insulating layer disposed on the substrate, a first conductive layer disposed on the first insulating layer, a second insulating layer disposed on the first conductive layer, and a second conductive layer disposed on the second insulating layer.Type: ApplicationFiled: March 12, 2014Publication date: March 5, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Teppei HIGASHITSUJI, Toshifumi MINAMI, Hideyuki KAMATA, Atsuhiro SATO, Keisuke YONEHAMA
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Patent number: 5561308Abstract: A semiconductor device comprises a semiconductor substrate of a first conductivity type, a first insulation film formed on the semiconductor substrate, a gate electrode and a second insulation film formed in sequence on the first insulation film, a trench being formed to extend through the second insulation film, the gate electrode and the first insulation film to an interior of the semiconductor substrate. A cylindrical gate insulation film is formed on a surface of the gate electrode which is exposed in the trench. A capacitor insulation film is formed on a surface of the semiconductor substrate exposed in the trench. A cylindrical conductive film is formed inside these insulation films.Type: GrantFiled: December 30, 1994Date of Patent: October 1, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Hideyuki Kamata, Jumpei Kumagai