Patents by Inventor Hideyuki Kanzawa

Hideyuki Kanzawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071773
    Abstract: Exemplary methods of semiconductor processing may include forming a layer of silicon-containing material on a semiconductor substrate. The methods may include performing a post-formation treatment on the layer of silicon-containing material to yield a treated layer of silicon-containing material. The methods may include contacting the treated layer of silicon-containing material with an adhesion agent. The methods may include forming a layer of a resist material on the treated layer of silicon-containing material.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 29, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Lei Liao, Yichuan Ling, Zhiyu Huang, Hideyuki Kanzawa, Fenglin Wang, Rajesh Prasad, Yung-Chen Lin, Chi-I Lang, Ho-yung David Hwang, Lequn Liu
  • Patent number: 7410897
    Abstract: A semiconductor device has anisotropically formed via holes through a PMD layer. The anisotropic geometry of the via holes results in the diameter of a via hole over a gate structure being equal to the diameter of a via hole not over the gate structure. The via holes are formed by depositing a silicon layer and an antireflective layer over the PMD layer. The silicon layer and the antireflective layer are etched to have holes with a regular taper. The holes through the PMD are anisotropically etched so as to have straight walls.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: August 12, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hideyuki Kanzawa
  • Patent number: 7169682
    Abstract: A method for manufacturing a semiconductor device comprising: a first step of successively forming a silicon oxide film and a silicon nitride film on a silicon substrate, followed by forming a silicon nitride oxide film or a multilayered film containing the silicon nitride oxide film on the silicon nitride film; a second step of forming a photoresist film having an opening portion located at the position corresponding to an element isolation area of the silicon substrate on the silicon nitride film or the multilayered film according to a photolithography method; a third step of forming a trench having a pair of tapered side surface portions on the confronting side surfaces thereof on the silicon nitride oxide film or the multilayered film by using the photoresist film as a mask, the tapered side surface portions being inclined toward the substrate side so as to approach each other; and a fourth step of patterning the silicon nitride film and the silicon oxide film by dry etching by using the photoresist fi
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: January 30, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuhiro Hirohama, Masaru Tanaka, Takayoshi Hashimoto, Shinichi Sato, Hideyuki Kanzawa
  • Patent number: 7122903
    Abstract: A semiconductor device has anisotropically formed via holes through a PMD layer. The anisotropic geometry of the via holes results in the diameter of a via hole over a gate structure being equal to the diameter of a via hole not over the gate structure. The via holes are formed by depositing a silicon layer and an antireflective layer over the PMD layer. The silicon layer and the antireflective layer are etched to have holes with a regular taper. The holes through the PMD are anisotropically etched so as to have straight walls.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: October 17, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hideyuki Kanzawa
  • Publication number: 20060091431
    Abstract: A semiconductor device has anisotropically formed via holes through a PMD layer. The anisotropic geometry of the via holes results in the diameter of a via hole over a gate structure being equal to the diameter of a via hole not over the gate structure. The via holes are formed by depositing a silicon layer and an antireflective layer over the PMD layer. The silicon layer and the antireflective layer are etched to have holes with a regular taper. The holes through the PMD are anisotropically etched so as to have straight walls.
    Type: Application
    Filed: December 9, 2005
    Publication date: May 4, 2006
    Inventor: Hideyuki Kanzawa
  • Publication number: 20050170607
    Abstract: A method for manufacturing a semiconductor device comprising: a first step of successively forming a silicon oxide film and a silicon nitride film on a silicon substrate, followed by forming a silicon nitride oxide film or a multilayered film containing the silicon nitride oxide film on the silicon nitride film; a second step of forming a photoresist film having an opening portion located at the position corresponding to an element isolation area of the silicon substrate on the silicon nitride film or the multilayered film according to a photolithography method; a third step of forming a trench having a pair of tapered side surface portions on the confronting side surfaces thereof on the silicon nitride oxide film or the multilayered film by using the photoresist film as a mask, the tapered side surface portions being inclined toward the substrate side so as to approach each other; and a fourth step of patterning the silicon nitride film and the silicon oxide film by dry etching by using the photoresist film
    Type: Application
    Filed: January 26, 2005
    Publication date: August 4, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kazuhiro Hirohama, Masaru Tanaka, Takayoshi Hashimoto, Shinichi Sato, Hideyuki Kanzawa
  • Publication number: 20050085086
    Abstract: A semiconductor device has anisotropically formed via holes through a PMD layer. The anisotropic geometry of the via holes results in the diameter of a via hole over a gate structure being equal to the diameter of a via hole not over the gate structure. The via holes are formed by depositing a silicon layer and an antireflective layer over the PMD layer. The silicon layer and the antireflective layer are etched to have holes with a regular taper. The holes through the PMD are anisotropically etched so as to have straight walls.
    Type: Application
    Filed: October 21, 2003
    Publication date: April 21, 2005
    Inventor: Hideyuki Kanzawa