Abstract: The grain-oriented electrical steel sheet according to the present embodiment is a grain-oriented electrical steel sheet having a base steel sheet (1), an intermediate layer (4) disposed to be in contact with the base steel sheet (1), and an insulation coating (3) disposed to be in contact with the intermediate layer (4). The grain-oriented electrical steel sheet according to the present embodiment includes a surface of the base steel sheet (1) having a strain region (D) which extends in a direction intersecting a rolling direction of the base steel sheet (1), and a crystalline phosphorus oxide M2P4O13 present in the insulation coating (3) on the strain region (D) in a cross-sectional view of a surface parallel to the rolling direction and a sheet thickness direction of the base steel sheet (1). (M means at least one or both of Fe and Cr.

Abstract: A printing apparatus includes a main body unit, a head unit that ejects ink onto a medium, a carriage that reciprocates with the head unit mounted on the main body unit, a support shaft that extends in a reciprocating direction of the carriage and supports the carriage, and a cable that has one end coupled to the main body unit and the other end electrically coupled to the head unit, and supplies an electrical signal to the head unit, the carriage includes a holder that holds the cable, and a plurality of supported portions that come into contact with the support shaft and are supported by the support shaft, and the holder is disposed at a position between at least two of the plurality of supported portions in the reciprocating direction.

Abstract: A semiconductor memory device comprises a first memory cell and a second memory cell. The semiconductor memory device is configured to be able to perform: a first operation which is a read operation or the like to the first memory cell; and a second operation which is a read operation or the like to the second memory cell. The semiconductor memory device transitions to a standby mode after performing the first operation in response to an input of a first command set and a second command set. The semiconductor memory device performs a charge share operation after the standby mode is released in response to an input of a third command set and a fourth command set during the standby mode. The semiconductor memory device performs the second operation using at least a part of an electric charge generated when the first operation is performed.

Abstract: A semiconductor storage device in an embodiment includes a plurality of planes each including a memory cell array, a voltage generation circuit configured to apply a first intermediate voltage to an adjacent word line adjacent to a selected word line in a former half of a program period and apply a second intermediate voltage higher than the first intermediate voltage to the adjacent word line in a latter half of the program period, a discharge circuit configured to feed a discharge current from the selected word line in a period corresponding to a period in which the second intermediate voltage is applied to the adjacent word line, and a control circuit configured to set a discharge characteristic of the discharge circuit according to a number of the planes.

Abstract: A semiconductor storage device includes a memory string including memory transistors and a control circuit. The control circuit is configured to in response to a first command, perform a first read operation, and in response to a second command received during the first read operation, perform a second read operation. During the first read operation, a voltage of a first selected word line is decreased from a read pass voltage to a first read voltage and then increased to the read pass voltage. During the second read operation, a voltage of a second word line is set to a second read voltage and then increased to the read pass voltage. Voltages of word lines neither selected during the first nor second read operation are maintained between the first and second read operations.

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

Abstract: According to one embodiment, a semiconductor memory device includes: first and second select transistors; first and second select gate lines; first and second interconnects; first and second memory cell transistors; and first and second word lines. In a write operation, after execution of a verify operation, in a period in which the second select transistor is ON, a voltage of the first word line changes from a first voltage to a second voltage and a voltage of the second word line changes from a third voltage applied in the verify operation to a fourth voltage, and after the voltage of the first word line changes to the second voltage and the voltage of the second word line changes to the fourth voltage, a voltage of the second select gate line changes from a fifth voltage to a sixth voltage.

Abstract: A semiconductor storage device includes a memory cell array having a plurality of first conductive layers stacked in a first direction and a plurality of memory cells connected to the plurality of first conductive layers, a wiring layer, and an insulating layer between the memory cell array and the wiring layer and separating the memory cell array and the wiring layer in a second direction intersecting the first direction. The wiring layer includes a plurality of second conductive layers stacked in the first direction, each of the second conductive layers having a corresponding first conductive layer at a same layer, and a contact connected to at least a part of the plurality of second conductive layers and extending in the first direction.

Abstract: A semiconductor storage device in an embodiment includes a plurality of planes each including a memory cell array, a voltage generation circuit configured to apply a first intermediate voltage to an adjacent word line adjacent to a selected word line in a former half of a program period and apply a second intermediate voltage higher than the first intermediate voltage to the adjacent word line in a latter half of the program period, a discharge circuit configured to feed a discharge current from the selected word line in a period corresponding to a period in which the second intermediate voltage is applied to the adjacent word line, and a control circuit configured to set a discharge characteristic of the discharge circuit according to a number of the planes.

Abstract: According to one embodiment, a semiconductor memory device includes: first and second select transistors; first and second select gate lines; first and second interconnects; first and second memory cell transistors; and first and second word lines. In a write operation, after execution of a verify operation, in a period in which the second select transistor is ON, a voltage of the first word line changes from a first voltage to a second voltage and a voltage of the second word line changes from a third voltage applied in the verify operation to a fourth voltage, and after the voltage of the first word line changes to the second voltage and the voltage of the second word line changes to the fourth voltage, a voltage of the second select gate line changes from a fifth voltage to a sixth voltage.

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

Abstract: A semiconductor memory device comprises a first memory cell array including a first memory cell and a second memory cell array including a second memory cell, a first transistor electrically connectable to a first end of the first memory cell via a first source line, a second transistor connectable to a first end of the second memory cell via a second source line, a pad supplied with a reference voltage from outside, a first wiring that electrically connects the first transistor and the pad, and a second wiring that is different from the first wiring and electrically connects the second transistor and the pad.

Abstract: A semiconductor memory device comprises a first memory cell array including a first memory cell and a second memory cell array including a second memory cell, a first transistor electrically connectable to a first end of the first memory cell via a first source line, a second transistor connectable to a first end of the second memory cell via a second source line, a pad supplied with a reference voltage from outside, a first wiring that electrically connects the first transistor and the pad, and a second wiring that is different from the first wiring and electrically connects the second transistor and the pad.

Abstract: A printer includes a transport unit that transports continuous paper, a medium support unit in which a support surface that is capable of supporting continuous paper that is transported by a transport unit, and first concave sections, which are indented from the support surface, are formed, and an image capture unit, which is disposed on a lower side of the support surface, and which captures an image of a lower surface of the continuous paper.

Abstract: A printer includes a transport unit that transports continuous paper, a medium support unit in which a support surface that is capable of supporting continuous paper that is transported by a transport unit, and first concave sections, which are indented from the support surface, are formed, and an image capture unit, which is disposed on a lower side of the support surface, and which captures an image of a lower surface of the continuous paper.

Abstract: A vibration generator including a coil, a plunger including a first shaft and a second shaft, and a frame. The first shaft is received in the coil such as to be movable in a first direction. The second shaft extends in a second direction orthogonal to the first direction, is disposed on the other side in the first direction relative to the coil with a gap therebetween. The first and second shafts are partly made of a magnetic material so as to be magnetically attractable to the coil and thereby movable to one side in the first direction. The frame is fixed to the first and second shafts at positions on the one and other sides, respectively, in the first direction relative to the coil, and elastically deformable at least partly as a result of movement of the first and second shafts.

Abstract: A printer includes a transport unit that transports continuous paper, a medium support unit in which a support surface that is capable of supporting continuous paper that is transported by a transport unit, and first concave sections, which are indented from the support surface, are formed, and an image capture unit, which is disposed on a lower side of the support surface, and which captures an image of a lower surface of the continuous paper.

Abstract: A printer includes a transport unit that transports continuous paper (P), a medium support unit (20) in which a support surface (20a) that is capable of supporting continuous paper (P) that is transported by a transport unit, and first concave sections (24A and 24B), which are indented from the support surface (20a), are formed, and an image capture unit, which is disposed on a lower side of the support surface (20a), and which captures an image of a lower surface of the continuous paper (P).