Patents by Inventor Hideyuki Kawakita

Hideyuki Kawakita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12082376
    Abstract: An electronic control device includes an enclosure including a first enclosure having an assembly opening and a second enclosure covering the entire assembly opening, the enclosure having a communication opening communicating with the assembly opening; a circuit board accommodated in the enclosure; an integrated circuit element mounted on the circuit board; and a heat dissipating shield member thermally coupled to the integrated circuit element and grounded, wherein the heat dissipating shield member includes an inner portion accommodated inside the enclosure and thermally coupled to the integrated circuit element and an outer portion extending to an outside of the enclosure via the communication opening.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: September 3, 2024
    Assignee: Hitachi Astemo, Ltd.
    Inventors: Minami Teranishi, Shinya Kawakita, Hideyuki Sakamoto
  • Patent number: 12058822
    Abstract: An electronic control device including a circuit substrate having a signal wiring and a ground wiring; at least one connector having a signal conductor and a ground conductor respectively connected to the signal wiring and the ground wiring of the circuit substrate on one end side and extending on the other end side; a housing including an accommodating portion that accommodates the circuit substrate and the at least one connector, in which a radio wave path through which a leakage electromagnetic wave propagates from one end on the circuit substrate side toward the other end on the side opposite to the circuit substrate side of the at least one connector is formed in an internal space at the periphery of the at least one connector; and a leakage electromagnetic wave attenuating structure provided between the housing and the at least one connector; where the leakage electromagnetic wave attenuating structure includes a plurality of conductors that are arrayed along a direction in which the leakage electromagn
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: August 6, 2024
    Assignee: HITACHI ASTEMO, LTD.
    Inventors: Yuki Nakamura, Masahiro Toyama, Hiroki Funato, Hideyuki Sakamoto, Shinya Kawakita
  • Publication number: 20100324877
    Abstract: A device property output apparatus includes an input unit configured to accept measured data of a device property, target data of the device property, and first simulation data indicating a simulation result of the device property, a reference data generator configured to generate reference data indicating a relationship between the measured data and the target data, a converter configured to conduct scale conversion of the first simulation data to generate second simulation data based on the reference data, and an output unit configured to output the second simulation data or auxiliary information indicating a difference between the target data and the second simulation data.
    Type: Application
    Filed: March 19, 2010
    Publication date: December 23, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hideyuki Kawakita
  • Patent number: 5930470
    Abstract: A target CPU executes a user program in synchronism with an asynchronous operation clock signal at higher speed than an operation clock signal of a debugging object system. A control unit portion outputs address bus information, data bus information, and machine cycle information in operation. A POD portion generates various control signals of the debugging object system based on the machine cycle information and then the address bus information, the data bus information, and the machine cycle information to the debugging object system in synchronism with an operation clock signal of the debugging object system. Collection, output, or process of debugging information can thus be executed by use of difference in execution times of the user program between the debugging object system and the target CPU, without halting the debugging object system.
    Type: Grant
    Filed: September 3, 1997
    Date of Patent: July 27, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoaki Noguchi, Hideyuki Kawakita