Patents by Inventor Hideyuki Kito

Hideyuki Kito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7731281
    Abstract: An impact absorbing plate 31 is disposed between a front part 31z of the impact absorbing plate 31 and a vehicle body 11 so that a rupture generating part 44 ruptured by impact is extended in the front and rear direction of the vehicle, and the impact absorbing plate 31 is fixed to a front part 13a and a rear part 13b of the front seat bracket 13 provided in the vehicle body by rivets 33 and 33. A portion of front part 31z of the impact absorbing plate 31 is cut to form a cutoff part 45, and a front end 17a of a rail 17 provided in a seat section is attached to a convex part 35, which is molded so as to expand upward an inner side of the cutoff part 45, by a rivet 34.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: June 8, 2010
    Assignees: Honda Motor Co., Ltd., Imasen Electric Industrial Co., Ltd.
    Inventors: Makoto Kurita, Koji Uno, Yukio Hiruta, Yoshiaki Morita, Masaru Ueda, Nobukatsu Masuda, Hideyuki Kito
  • Publication number: 20070273186
    Abstract: An impact absorbing plate 31 is disposed between a front part 31z of the impact absorbing plate 31 and a vehicle body 11 so that a rupture generating part 44 ruptured by impact is extended in the front and rear direction of the vehicle, and the impact absorbing plate 31 is fixed to a front part 13a and a rear part 13b of the front seat bracket 13 provided in the vehicle body by rivets 33 and 33. A portion of front part 31z of the impact absorbing plate 31 is cut to form a cutoff part 45, and a front end 17a of a rail 17 provided in a seat section is attached to a convex part 35, which is molded so as to expand upward an inner side of the cutoff part 45, by a rivet 34.
    Type: Application
    Filed: May 21, 2007
    Publication date: November 29, 2007
    Applicants: Honda Motor Co., Ltd., Imasen Electrical Industrial Co., Ltd.
    Inventors: Makoto Kurita, Koji Uno, Yukio Hiruta, Yoshiaki Morita, Masaru Ueda, Nobukatsu Masuda, Hideyuki Kito
  • Patent number: 6878632
    Abstract: A semiconductor device capable of suppressing diffusion of copper at an interface between a copper wire and a cap film to enhance an electromigration resistance to ensure reliability of the copper wire, and a manufacturing method thereof are provided. The semiconductor device according to the present invention comprises an insulating film (12) formed on a substrate (11), a concave portion (13) (for example, a groove) formed in the insulating film, a conductive layer (15) embedded in the concave portion through a barrier layer (14), and a cobalt tungsten phosphorus coating (16) to connect with the barrier layer on the side of the conductive layer and to coat the conductive layer on the opening side of the concave portion.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: April 12, 2005
    Assignee: Sony Corporation
    Inventors: Takeshi Nogami, Naoki Komai, Hideyuki Kito, Mitsuru Taguchi
  • Publication number: 20040188273
    Abstract: An electrolytic polishing apparatus for electrolytic-polishing a conductive film subject to formed on a substrate including a resistance measuring unit for measuring the resistance of the film. The electrolytic polishing apparatus may also include a termination point detecting portion for detecting a termination point of polishing by reading a variation of the resistance value measured by the resistance measuring unit, or a polishing control portion for terminating electrolytic polishing on the basis of the termination point of polishing detected by the termination point detecting portion.
    Type: Application
    Filed: April 13, 2004
    Publication date: September 30, 2004
    Inventors: Takeshi Nogami, Naoki Komai, Hideyuki Kito, Mitsuru Taguchi
  • Patent number: 6736699
    Abstract: An electrolytic polishing apparatus for electrolytic-polishing a conductive film subject to formed on a substrate including a resistance measuring unit for measuring the resistance of the film. The electrolytic polishing apparatus may also include a termination point detecting portion for detecting a termination point of polishing by reading a variation of the resistance value measured by the resistance measuring unit, or a polishing control portion for terminating electrolytic polishing on the basis of the termination point of polishing detected by the termination point detecting portion.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: May 18, 2004
    Assignee: Sony Corporation
    Inventors: Takeshi Nogami, Naoki Komai, Hideyuki Kito, Mitsuru Taguchi
  • Patent number: 6709979
    Abstract: A method of implementing an electrolytic polishing process against a wiring-material film by way of preventing excessive polishing or incomplete polishing caused by presence of differential steps locally generated in the objective wiring-material film. The inventive method comprises a step of forming a wiring-material film for burying recessed portions formed on an insulating film formed on a substrate via a plating process; a step of reducing a local differential step generated on the surface of the wiring-material film by way of preserving the wiring material film on the insulating film; and a final step of removing the wiring-material film deposited on the insulating film by way of preserving such wiring-material film deposited, solely inside of the recessed portions.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: March 23, 2004
    Assignee: Sony Corporation
    Inventors: Naoki Komai, Takeshi Nogami, Hideyuki Kito, Mitsuru Taguchi, Katsumi Ando
  • Patent number: 6602787
    Abstract: The present invention is to provide a method for fabricating semiconductor devices capable of eliminating a height difference on a base member caused by a residual plating seed layer remained in a portion where an electrode comes into contact and is thus prevented from contacting with an electrolytic polishing fluid, where such height difference has been a problem in introducing the electrolytic polishing process into wafer process. The method comprises the steps of forming a plating seed layer on the base member; forming by the plating process a plated film on the plating seed layer in an area excluding the outer peripheral portion of the base member; polishing the plated film together with the plating seed layer by the electrolytic polishing process; and selectively removing the plating seed layer remaining on the outer peripheral portion of the base member.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: August 5, 2003
    Assignee: Sony Corporation
    Inventors: Naoki Komai, Takeshi Nogami, Hideyuki Kito, Mitsuru Taguchi
  • Publication number: 20030119317
    Abstract: A semiconductor device capable of suppressing diffusion of copper at an interface between a copper wire and a cap film to enhance an electromigration resistance to ensure reliability of the copper wire, and a manufacturing method thereof are provided. The semiconductor device according to the present invention comprises an insulating film (12) formed on a substrate (11), a concave portion (13) (for example, a groove) formed in the insulating film, a conductive layer (15) embedded in the concave portion through a barrier layer (14), and a cobalt tungsten phosphorus coating (16) to connect with the barrier layer on the side of the conductive layer and to coat the conductive layer on the opening side of the concave portion.
    Type: Application
    Filed: October 7, 2002
    Publication date: June 26, 2003
    Inventors: Takeshi Nogami, Naoki Komai, Hideyuki Kito, Mitsuru Taguchi
  • Publication number: 20020090884
    Abstract: An electrolytic polishing apparatus for electrolytic-polishing a conductive film subject to formed on a substrate including a resistance measuring unit for measuring the resistance of the film. The electrolytic polishing apparatus may also include a termination point detecting portion for detecting a termination point of polishing by reading a variation of the resistance value measured by the resistance measuring unit, or a polishing control portion for terminating electrolytic polishing on the basis of the termination point of polishing detected by the termination point detecting portion.
    Type: Application
    Filed: August 3, 2001
    Publication date: July 11, 2002
    Inventors: Takeshi Nogami, Naoki Komai, Hideyuki Kito, Mitsuru Taguchi
  • Publication number: 20020074664
    Abstract: On a copper wiring surface, an oxidation resistive and fluorinated acid resistive layer is formed, and an oxidation resistive copper wiring, enhancement of resistive fluorinated acid nature are achieved. Furthermore, a via-hole connection resistance is reduced, and a clad layer (the CoWP layer) having oxidation resistive and fluorinated acid resistive nature high copper wiring configuration is formed, and cover layer (the CoWP layer) including cobalt and the CoWP layer of reliability, and the CoWP layer is formed by the copper wiring.
    Type: Application
    Filed: July 25, 2001
    Publication date: June 20, 2002
    Inventors: Takeshi Nogami, Naoki Komai, Hideyuki Kito, Mitsuru Taguchi
  • Patent number: 6407011
    Abstract: A stacked insulating film having an organic insulating film, and a carbon-containing silicon oxide film formed on the organic insulating film is disclosed. The carbon-containing silicon oxide film has a carbon content of 8 atom % to 25 atom %.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: June 18, 2002
    Assignee: Sony Corporation
    Inventors: Koichi Ikeda, Masanaga Fukasawa, Hideyuki Kito, Toshiaki Hasegawa
  • Publication number: 20020068438
    Abstract: The present invention is to provide a method for fabricating semiconductor devices capable of eliminating a height difference on a base member caused by a residual plating seed layer remained in a portion where an electrode comes into contact and is thus prevented from contacting with an electrolytic polishing fluid, where such height difference has been a problem in introducing the electrolytic polishing process into wafer process. The method comprises the steps of forming a plating seed layer on the base member; forming by the plating process a plated film on the plating seed layer in an area excluding the outer peripheral portion of the base member; polishing the plated film together with the plating seed layer by the electrolytic polishing process; and selectively removing the plating seed layer remaining on the outer peripheral portion of the base member.
    Type: Application
    Filed: June 12, 2001
    Publication date: June 6, 2002
    Inventors: Naoki Komai, Takeshi Nogami, Hideyuki Kito, Mitsuru Taguchi
  • Patent number: 6383907
    Abstract: A process for producing a semiconductor device comprising an interlayer dielectric containing an organic film, which process comprises the step of forming on the interlayer dielectric a three-layer mask comprising a first mask, a second mask and a third mask in this order from the bottom, in which the first mask, the second mask and the third mask are made of materials different from one another, and the second mask is formed from a film made of a material which protects a film for forming the first mask during formation of the third mask.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: May 7, 2002
    Assignee: Sony Corporation
    Inventors: Toshiaki Hasegawa, Koichi Ikeda, Hideyuki Kito
  • Publication number: 20020016064
    Abstract: A method of implementing an electrolytic polishing process against a wiring-material film by way of preventing excessive polishing or incomplete polishing caused by presence of differential steps locally generated in the objective wiring-material film. The inventive method comprises a step of forming a wiring-material film for burying recessed portions formed on an insulating film formed on a substrate via a plating process; a step of reducing a local differential step generated on the surface of the wiring-material film by way of preserving the wiring material film on the insulating film; and a final step of removing the wiring-material film deposited on the insulating film by way of preserving such wiring-material film deposited, solely inside of the recessed portions.
    Type: Application
    Filed: May 29, 2001
    Publication date: February 7, 2002
    Inventors: Naoki Komai, Takeshi Nogami, Hideyuki Kito, Mitsuru Taguchi, Katsumi Ando
  • Patent number: 5578530
    Abstract: In a manufacturing method of semiconductor device having a fluorine-containing SiN layer, an SiN layer excellent in the step coverage can be formed using as raw material an Si compound containing at least both nitrogen and fluorine, by virtue of an intermediate product which, during the formation of the above SiN layer, is formed, liable to polymerization and has fluidity. Moreover, as the above Si compound contains fluorine that is taken into the formation of the fluorine-containing SiN layer whose dielectric constant is lowered thereby, delay in circuit operation due to parasitic capacitances can be reduced.
    Type: Grant
    Filed: July 12, 1995
    Date of Patent: November 26, 1996
    Assignee: Sony Corporation
    Inventors: Masakazu Muroyama, Hideyuki Kito