Patents by Inventor Hideyuki Koinuma
Hideyuki Koinuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9652299Abstract: A hardware thread causes a SleepID register of a WAKEUP signal generation unit to store a SleepID that identifies the hardware thread when suspending a process due to waiting for a process by another CPU. The WAKEUP signal generation unit causes the WAKEUP data register of the WAKEUP signal generation unit to store a SleepID notified by a node when a process that the hardware thread waits ends. The WAKEUP signal generation unit outputs a WAKEUP signal that cancels the stop of the hardware thread to the hardware thread when the SleepIDs of the SleepID register and the WAKEUP data register agree with each other.Type: GrantFiled: October 17, 2012Date of Patent: May 16, 2017Assignee: FUJITSU LIMITEDInventors: Hideyuki Koinuma, Hideyuki Kizawa, Keiji Miyauchi
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Patent number: 9065706Abstract: An abnormality detection unit provided in at least one node among a plurality of nodes included in an information processing apparatus detects abnormality in a data transmission path of data transmission using a shared memory area sharable in a single node and other node, which is included in the storage unit provided in the single node or other nodes. An error information generation unit provided in the single node generates error information, based on the abnormality detected by the abnormality detection unit, and generates an interrupt with respect to a processor within a self node. The processor provided in the single node performs recovery processing, based on the error information according to the interrupt.Type: GrantFiled: September 12, 2012Date of Patent: June 23, 2015Assignee: FUJITSU LIMITEDInventors: Hideyuki Koinuma, Go Sugizaki, Toshikazu Ueki
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Patent number: 9003082Abstract: An information processing apparatus including a plurality of nodes. The each of the nodes comprises a processor, a storage device, and a storing unit that stores therein multiple pointer sets in each of which a write pointer indicating an address used when data received from another node is stored in the storage device is associated with a read pointer indicating an address used when the data is read from the storage device. The each of the nodes comprises a notifying unit that notifies a node corresponding to a transmission source of the data of a pointer identifier that indicates a pointer set. The each of the nodes comprises a retaining unit that retains the received data in the storage device in accordance with an address indicated by a write pointer in a pointer set indicated by the pointer identifier.Type: GrantFiled: August 30, 2012Date of Patent: April 7, 2015Assignee: Fujitsu LimitedInventors: Seishi Okada, Toshikazu Ueki, Hideyuki Koinuma
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Patent number: 8856588Abstract: At least one node of a plurality of nodes in an information processing apparatus executes the following processing for data included in a memory of one node or other nodes and stored in a shared memory area which the node and the other nodes access. That is, the node detects an ICE which occurs over a predetermined number of times within a predetermined time or a PCE which occurs at a single location in the shared memory area. When the error is detected, the node performs control to prevent the node and the other nodes from accessing the shared memory. The node recovers the data in a memory area different from the shared memory area. The node notifies information about the different memory area to the other nodes. The node performs control to resume the access to the data from the node and the other nodes.Type: GrantFiled: August 29, 2012Date of Patent: October 7, 2014Assignee: Fujitsu LimitedInventors: Hideyuki Koinuma, Hiroyuki Izui
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Publication number: 20140068299Abstract: When a result of detection by a current sensor 22 represents the occurrence of an overcurrent, comparators 23 of PSUs 2 transmit a present report indicating that fact to an SP 1. Receiving the present report, an FPGA 12 of the SP 1 turns on a forcible low-power signal. A forcible power saving control circuit 32 of a CPU 3 directly inputs a forcible-low-power-mode signal, turns on the signal, and controls an instruction issuance control unit that is configured to issue an instruction in the CPU 3, so as to immediately decrease the frequency at which the instruction issuance control unit issues instructions. This control is cancelled after the DVFS control circuit 35 has reduced the voltage of power output from a DDC 4 and a clock frequency output from a PLL circuit.Type: ApplicationFiled: August 27, 2013Publication date: March 6, 2014Applicant: FUJITSU LIMITEDInventors: HIDEYUKI KOINUMA, HIROMI FUKUMURA, MICHIHARU HARA, HIRONOBU KAGEYAMA, TOSHIO YOSHIDA
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Publication number: 20130262783Abstract: An information processing apparatus including a plurarity of nodes. The each of the nodes comprises a processor, a storage device, and a storing unit that stores therein multiple pointer sets in each of which a write pointer indicating an address used when data received from another node is stored in the storage device is associated with a read pointer indicating an address used when the data is read from the storage device. The each of the nodes comprises a notifying unit that notifies a node corresponding to a transmission source of the data of a pointer identifier that indicates a pointer set. The each of the nodes comprises a retaining unit that retains the received data in the storage device in accordance with an address indicated by a write pointer in a pointer set indicated by the pointer identifier.Type: ApplicationFiled: August 30, 2012Publication date: October 3, 2013Applicant: FUJITSU LIMITEDInventors: Seishi OKADA, Toshikazu Ueki, Hideyuki Koinuma
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Publication number: 20130227224Abstract: At least one node of a plurality of nodes in an information processing apparatus executes the following processing for data included in a memory of one node or other nodes and stored in a shared memory area which the node and the other nodes access. That is, the node detects an ICE which occurs over a predetermined number of times within a predetermined time or a PCE which occurs at a single location in the shared memory area. When the error is detected, the node performs control to prevent the node and the other nodes from accessing the shared memory. The node recovers the data in a memory area different from the shared memory area. The node notifies information about the different memory area to the other nodes. The node performs control to resume the access to the data from the node and the other nodes.Type: ApplicationFiled: August 29, 2012Publication date: August 29, 2013Applicant: FUJITSU LIMITEDInventors: Hideyuki Koinuma, Hiroyuki Izui
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Patent number: 8521977Abstract: An information processing apparatus includes nodes having a first node and a second node each of which includes a processor and a memory in which at least a part of area is set as a shared memory area, and an interconnect that connects the nodes. The first node transmits communication data to be transmitted to the second node by attaching identification information used for accessing a memory in the second node. The second node determines whether or not an access to the shared memory area in the memory in the second node is permitted on the basis of the identification information that is attached to the communication data transmitted from the first node and identification information stored in a storing unit and used for controlling permission to access, from another node, the shared memory area in the memory in the second node.Type: GrantFiled: October 17, 2012Date of Patent: August 27, 2013Assignee: Fujitsu LimitedInventors: Toshikazu Ueki, Seishi Okada, Hideyuki Koinuma, Go Sugizaki
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Publication number: 20130170334Abstract: An abnormality detection unit provided in at least one node among a plurality of nodes included in an information processing apparatus detects abnormality in a data transmission path of data transmission using a shared memory area sharable in a single node and other node, which is included in the storage unit provided in the single node or other nodes. An error information generation unit provided in the single node generates error information, based on the abnormality detected by the abnormality detection unit, and generates an interrupt with respect to a processor within a self node. The processor provided in the single node performs recovery processing, based on the error information according to the interrupt.Type: ApplicationFiled: September 12, 2012Publication date: July 4, 2013Applicant: FUJITSU LIMITEDInventors: Hideyuki Koinuma, Go Sugizaki, Toshikazu Ueki
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Publication number: 20130174224Abstract: An information processing apparatus includes nodes having a first node and a second node each of which includes a processor and a memory in which at least a part of area is set as a shared memory area, and an interconnect that connects the nodes. The first node transmits communication data to be transmitted to the second node by attaching identification information used for accessing a memory in the second node. The second node determines whether or not an access to the shared memory area in the memory in the second node is permitted on the basis of the identification information that is attached to the communication data transmitted from the first node and identification information stored in a storing unit and used for controlling permission to access, from another node, the shared memory area in the memory in the second node.Type: ApplicationFiled: September 7, 2012Publication date: July 4, 2013Applicant: FUJITSU LIMITEDInventors: Toshikazu UEKI, Seishi Okada, Hideyuki Koinuma, Go Sugizaki
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Publication number: 20130159638Abstract: A node includes a first converting unit that performs conversion between a logical address and a physical address. The node includes a second converting unit that performs conversion between the physical address and processor identification information for identifying a processor included in a each of a plurality of nodes. The node includes a transmitting unit that transmits transmission data including the physical address and the processor identification information for accessing a storing area indicated by the physical address. The node includes a local determining unit that determines whether an access, indicated by the transmission data received from another nodes, is an access to a local area or an access to a shared area based on the physical address included in the transmission data received by the receiving unit.Type: ApplicationFiled: September 10, 2012Publication date: June 20, 2013Applicant: FUJITSU LIMITEDInventors: Hideyuki Koinuma, Seishi Okada, Go Sugizaki
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Patent number: 8166273Abstract: By including detecting an abnormality in a first system common unit; reading a priority indication, from the storage portion, indicating whether or not the first system common unit is to be degenerated when an abnormality occurs in the first system common unit for each of the partitioned portions; carrying out, when an abnormality is detected in a partitioned portion to which the priority indication is set, suspend processing on the information processing apparatus by the system control portion on the partitioned portion; and carrying out degeneration processing for suspending operation of the first system common unit and switching to the second system common unit, quick recovery is achieved when a significant partition is down due to a fault experienced in a common unit.Type: GrantFiled: July 20, 2009Date of Patent: April 24, 2012Assignee: Fujitsu LimitedInventor: Hideyuki Koinuma
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Publication number: 20090292897Abstract: By including detecting an abnormality in a first system common unit; reading a priority indication, from the storage portion, indicating whether or not the first system common unit is to be degenerated when an abnormality occurs in the first system common unit for each of the partitioned portions; carrying out, when an abnormality is detected in a partitioned portion to which the priority indication is set, suspend processing on the information processing apparatus by the system control portion on the partitioned portion; and carrying out degeneration processing for suspending operation of the first system common unit and switching to the second system common unit, quick recovery is achieved when a significant partition is down due to a fault experienced in a common unit.Type: ApplicationFiled: July 20, 2009Publication date: November 26, 2009Inventor: Hideyuki KOINUMA
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Publication number: 20080282113Abstract: A failure information management method manages failure information related to a replaceable part of an electronic apparatus, by generating an error log, and storing the error log in a non-volatile memory of the replacement recommended part itself. The error log is generated by recording first generation information in a representative log information part and detailed log information part in a non-overwritable manner with respect to a first failure of a replacement recommended part, and by recording second generation information in the representative log information part and the detailed log information part in an overwritable manner with respect to second and subsequent failures of the replacement recommended part.Type: ApplicationFiled: July 17, 2008Publication date: November 13, 2008Applicant: FUJITSU LIMITEDInventors: Kazuhiro Yuuki, Kenji Okano, Hideyuki Koinuma, Kenji Korekata, Hiroyuki Watanabe
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Patent number: 6247063Abstract: A LAN terminal equipment comprises a plurality of slots, each capable of accommodating a LAN control board, at least one ROM socket capable of holding a MAC ROM, and an input/output control unit. The input/output control unit determines a correspondence between the LAN control board and the MAC ROM, thereby ensuring the uniqueness of MAC address and also making a primary/spare dual configuration possible.Type: GrantFiled: July 1, 1998Date of Patent: June 12, 2001Assignee: Fujitsu LimitedInventors: Masahiro Ichimi, Kenichi Mori, Hideyuki Koinuma
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Patent number: 6058446Abstract: A LAN terminal equipment comprises a plurality of slots, each capable of accommodating a LAN control board, at least one ROM socket capable of holding a MAC ROM, and an input/output control unit. The input/output control unit determines a correspondence between the LAN control board and the MAC ROM, thereby ensuring the uniqueness of MAC address and also making a primary/spare dual configuration possible.Type: GrantFiled: January 17, 1996Date of Patent: May 2, 2000Assignee: Fujitsu LimitedInventors: Masahiro Ichimi, Kenichi Mori, Hideyuki Koinuma